Buried oxide with a thermal expansion matching layer for SOI

• US 6,045,625 A
• Filed: 12/05/1997
• Issued: 04/04/2000
• Est. Priority Date: 12/06/1996
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Houston, Theodore W.
• Primary Examiner(s): FOURSON III, GEORGE R
• Application Number:
  US08/985,697
• Time in Patent Office: 851 Days
• Field of Search: 438/406, 438/455, 438/459, 438/FOR 222, 148/DIG. 12, 148/DIG. 50, 148/DIG. 85, 148/DIG. 86, 148/33.3, 257/505, 257/499, 257/506
• US Class Current: 148/33.3
• CPC Class Codes: H01L 21/76264 SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
• CPC Class Codes: H01L 21/76283 Lateral isolation by refilling of trenches with dielectric material
• CPC Class Codes: H01L 21/76286 Lateral isolation by refilling of trenches with polycristalline material
• CPC Class Codes: H01L 29/02 Semiconductor bodies ; Multistep manufacturing processes therefor

Abstract

A silicon-on-insulator structure (10) having a thick buried multi-layer (14) is disclosed herein. The thick buried multi-layer (14) comprises a thermal expansion coefficient matching layer (14b) between two insulator layers (14a,14c). The thermal expansion co-efficient matching layer (14b) comprises a material that more closely matches the thermal expansion co-efficient of the silicon substrate (12). Examples include polysilicon and nitridized oxide.

Claims

1. A silicon-on-insulator structure, comprising:

a substrate;

a device layer comprising silicon; and

a buried insulating layer between the substrate and device layer, said buried insulating layer comprising a first dielectric layer adjacent said substrate, a layer of silicon adjacent said first dielectric layer, and a second dielectric layer adjacent said device layer, wherein said layer of silicon comprises an implanted region.

2. The structure of claim 1, wherein said layer of silicon comprises an isolation trench laterally adjacent said implanted region.

3. The structure of claim 1, wherein a portion of said silicon layer extends through said first dielectric layer to connect to said substrate.

4. The structure of claim 1, wherein a portion of said silicon layer extends through said first dielectric layer to connect to said device layer.

5. The structure of claim 1, further comprising a silicide layer on a portion of said silicon layer.

6. The structure of claim 1, further comprising a contact extending from said device layer through said insulating layer to said substrate.

7. The structure of claim 6, further comprising silicide in said contact adjacent said substrate and sidewalls of said silicon layer.

8. The structure of claim 1, wherein said layer of silicon comprises polysilicon.

9. The structure of claim 1, wherein said layer of silicon comprises amorphous silicon.

10. The structure of claim 1, wherein said insulating layer is greater than 2 μ

m thick.

11. A silicon-on-insulator structure, comprising:

a substrate;

a device layer;

an electrically insulating layer between said substrate and said device layer, said electrically insulating layer comprising;

a first layer of oxide adjacent said substrate;

a layer of silicon adjacent said first oxide layer;

a second layer of oxide located on an opposite side of said silicon layer from said first layer of oxide between said layer of silicon and said device layer.

12. The structure of claim 11, wherein said silicon layer comprises:

a layer of polysilicon.

13. The structure of claim 11, wherein said layer of polysilicon is thicker than said first and second layers of oxide.

14. The structure of claim 11, wherein said silicon layer comprises:

a layer of amorphous silicon.

15. A silicon-on-insulator structure, comprising:

a substrate;

a device layer comprising silicon;

a buried insulating layer between the substrate and device layer, said buried insulating layer comprising a first dielectric layer adjacent said substrate, a layer of silicon adjacent said first dielectric layer, and a second dielectric layer adjacent said device layer; and

a contact extending from said device layer through said insulating layer to said substrate, said contact having silicide in said contact adjacent said substrate and sidewalls of said silicon layer.