High tensile nitride layer

• US 6,046,494 A
• Filed: 01/31/1997
• Issued: 04/04/2000
• Est. Priority Date: 09/30/1994
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Lee, Yung-Huei, Chau, Robert S., Brigham, Lawrence N., Cotner, Raymond E.
• Primary Examiner(s): Meier, Stephen D.
• Application Number:
  US08/791,867
• Time in Patent Office: 1,159 Days
• Field of Search: 257/640, 257/412, 257/413
• US Class Current: 257/640
• CPC Class Codes: H01L 21/02129 the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/02211 the compound being a silane, e.g. disilane, methylsilane or chlorosilane
• CPC Class Codes: H01L 21/02216 the compound being a molecule comprising at least one silicon-oxygen bond and the compound having hydrogen or an organic group attached to the silicon or oxygen, e.g. a siloxane
• CPC Class Codes: H01L 21/02271 deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition H01L21/02266 takes precedence
• CPC Class Codes: H01L 21/3185 of siliconnitrides
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer
• CPC Class Codes: Y10S 438/954 Making oxide-nitride-oxide device

Abstract

An insulating layer in a semiconductor device and a process for forming the insulating layer is described. The insulating layer comprises of a nitride layer over the substrate having a residual stress of between -8×10⁹ dynes/cm^-2 and -3×10¹⁰ dynes/cm^-2. The insulating layer can further comprise a doped oxide layer under the nitride layer and can further comprise an interlevel dielectric layer over the nitride layer. Moreover, the nitride layer can be formed by bringing the temperature in a chemical vapor deposition reactor to below 550 degrees Celsius, placing the substrate into the reactor at the temperature, and forming the nitride layer on the substrate. Alternatively, the nitride layer can be formed by pushing the substrate into a chemical vapor deposition reactor at a speed greater than 300 millimeters per minute, and forming the nitride layer on the substrate.

Claims

1. An insulating layer in a semiconductor device comprising:

a doped oxide layer on a doped region of said semiconductor devices;

a nitride film having a residual stress of between -8×

10¹⁰ dynes/cm² and 3×

10¹⁰ dynes/cm² formed on said doped oxide layer; and

an interlayer dielectric layer on said nitride film.

2. A semiconductor device comprising:

a silicide layer;

a refractory metal oxysilicide layer having a thickness of less than 100 angstroms over said silicide layer; and

a nitride layer on said refractory metal oxysilicide layer; and

an interlayer dielectric on said nitride layer.

3. A field effect transistor comprising:

a source region;

a drain region coupled to said source region;

a silicide layer;

a refractory metal oxysilicide layer having a thickness of less than 100 angstroms;

a nitride layer over said refractory metal oxysilicide layer having a residual stress of between -8×

10⁹ dynes /cm² and -3×

10¹⁰ dynes/cm² ; and

an interlevel dielectric layer over said nitride layer.

4. An integrated circuit comprising:

a device having a silicide layer;

a doped oxide layer on said silicide layer;

a nitride layer having a tensile stress on said doped oxide layer; and

an interlayer dielectric on said nitride layer.

5. An integrated circuit comprising:

a transistor on a semiconductor substrate, said transistor having at least one silicide region;

a doped oxide layer on said transistor including said silicide region;

a nitride layer having a tensile stress on said doped oxide layer; and

an interlayer dielectric on said nitride layer.

6. The integrated circuit of claim 5 wherein said doped oxide layer is a phosphorus doped oxide layer.

7. The integrated circuit of claim 5 wherein said doped oxide layer is a boron doped oxide layer.

8. The integrated circuit of claim 5 wherein said nitride layer has a tensile stress between 8×

10⁹ dynes/cm² and 3×

10¹⁰ dynes/cm².

9. An integrated circuit comprising:

a transistor having a source, a gate and a drain;

a refractory silicide on said source and said drain;

a doped oxide layer on said transistor and on said refractory metal silicide and on said source and said drain;

a nitride layer having a residual tensile stress on said doped oxide layer; and

an interlayer dielectric on said nitride layer.

10. The integrated circuit of claim 9 wherein said transistor is a PMOS transistor and said doped oxide layer is a boron doped oxide layer.

11. The integrated circuit of claim 9 wherein said transistor is a NMOS transistor and said doped oxide layer is a phosphorus doped oxide layer.

12. The integrated circuit of claim 9 wherein said nitride layer has a tensile stress of between 8×

10⁹ dynes/cm² and 3×

10¹⁰ dynes/cm².