Method and apparatus for controlling the partial reconfiguration of a field programmable gate array

• US 6,046,603 A
• Filed: 12/12/1997
• Issued: 04/04/2000
• Est. Priority Date: 12/12/1997
• Status: Expired due to Term

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: New, Bernard J.
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): CHO, JAMES HYONCHOL
• Application Number:
  US08/989,980
• Time in Patent Office: 844 Days
• Field of Search: 326/38-41, 326/47
• US Class Current: 326/38
• CPC Class Codes: H03K 19/17752 for hot reconfiguration
• CPC Class Codes: H03K 19/17756 for partial configuration or partial reconfiguration
• CPC Class Codes: H03K 19/17758 for speeding up configuration or reconfiguration

Abstract

A field programmable gate array (FPGA) having an array of configurable logic blocks (CLBs) which can be partially reconfigured. Each column of CLBs is connected to a corresponding column select line, and each row of CLBs is connected to a corresponding row select line. A rectangular set of CLBs to be reconfigured is selected, wherein the rectangular set of CLBs is defined by the intersection of one or more consecutive columns of CLBs and one or more consecutive rows of CLBs. Column select signals are asserted on the column select lines associated with the one or more consecutive columns of CLBs. Similarly, row select signals are asserted on the row select lines associated with the one or more consecutive rows of CLBs. CLBs which receive both an asserted column select signal and an asserted row select signal are enabled for reconfiguration.

Claims

1. A method for partially reconfiguring an array of configurable logic blocks (CLBs) arranged in a plurality of rows and columns, the method comprising the steps of:

connecting each column of CLBs to a corresponding column select line;

connecting each row of CLBs to a corresponding row select line;

selecting a rectangular set of CLBs to be reconfigured, wherein the rectangular set of CLBs is defined by the intersection of one or more consecutive columns of CLBs and one or more consecutive rows of CLBs;

asserting column select signals on the column select lines associated with the one or more consecutive columns of CLBs;

asserting row select signals on the row select lines associated with the one or more consecutive rows of CLBs; and

enabling reconfiguration circuits within each CLB which receives both an asserted column select signal and an asserted row select signal;

wherein the step of asserting the column select signals further comprises the steps of;

asserting a first column select signal on a first column select line;

propagating the first column select signal to one or more consecutive column select lines; and

generating a control signal for stopping the propagation of the first column select signal.

2. The method of claim 1, wherein the step of asserting the row select signals further comprises the steps of:

asserting a first row select signal on a first row select line;

propagating the first row select signal to one or more consecutive row select lines; and

generating a control signal for stopping the propagation of the first row select signal.

3. A method of reconfiguring a field programmable gate array having an array of configurable logic blocks (CLBs), the method comprising the steps of:

selecting a block of CLBs within the array of CLBs for reconfiguration, the block of CLBs being defined by one or more consecutive rows beginning with a first row and ending with a second row, and one or more consecutive columns beginning with a first column and ending with a second column;

addressing the first row to generate a row select signal which is asserted at the first row and propagates toward the second row;

addressing the first column to generate a column select signal which is asserted at the first column and propagates toward the second column;

addressing the row immediately following the second row, thereby stopping the propagation of the row select signal at the second row;

addressing the column immediately following the second column, thereby stopping the propagation of the column select signal at the second column; and

reconfiguring each CLB which receives both the column select signal and the row select signal.

4. A field programmable gate array (FPGA) comprising:

an array of configurable logic blocks (CLBs) arranged in a plurality of rows and columns, wherein each of the CLBs includes a reconfiguration circuit for reconfiguring the CLB, and an enabling circuit for enabling the reconfiguration circuit;

a plurality of column select lines, wherein each of the column select lines is coupled to each of the enabling circuits in a corresponding column of the CLBs;

a plurality of row select lines, wherein each of the row select lines is coupled to each of the enabling circuits in a corresponding row of the CLBs;

a column select circuit coupled to each of the column select lines, wherein the column select circuit comprises a plurality of cascaded exclusive OR gates, wherein each of the exclusive OR gates has an output terminal which is coupled to a corresponding column select line, wherein the column select circuit is controlled to assert column select signals on one or more consecutive column select lines; and

a row select circuit coupled to each of the row select lines, wherein the row select circuit is controlled to assert row select signals on one or more consecutive row select lines, wherein the enabling circuits that receive both a column select signal and a row select signal enable the associated reconfiguration circuits.

5. The FPGA of claim 4, wherein the column select circuit further comprises:

a plurality of flip flops, wherein each flip flop has an input terminal coupled to receive a logic signal having a first state, and an output terminal coupled to an input terminal of a corresponding one of the exclusive OR gates; and

a plurality of address decoders each having a unique associated address, each of the address decoders having an output terminal coupled to a load input terminal of a corresponding one of the flip flops, and each of the address decoders having input terminals coupled to receive an address signal.

6. The FPGA of claim 5, wherein the exclusive OR gate coupled to the column select line associated with the first column of CLBs has an input terminal coupled to receive a logic signal having a second state.

7. The FPGA of claim 5, wherein the row select circuit further comprises:

a plurality of flip flops, wherein each flip flop has an input terminal coupled to receive a logic signal having the first state, and an output terminal coupled to an input terminal of a corresponding one of the exclusive OR gates of the row select circuit; and

a plurality of address decoders, each having a unique associated address, each of the address decoders having an output terminal coupled to a load input terminal of a corresponding one of the flip flops of the row select circuit, and each of the address decoders having input terminals coupled to receive an address signal.

8. The FPGA of claim 4, wherein the row select circuit comprises a plurality of cascaded exclusive OR gates, wherein each of the exclusive OR gates of the row select circuit has an output terminal which is coupled to a corresponding row select line.

9. The FPGA circuit of claim 4, wherein the column select circuit further comprises:

a plurality of OR gates, wherein each of the OR gates has an output terminal coupled to an input terminal of a corresponding one of the exclusive OR gates;

a plurality of flip flops, wherein each of the flip flops has an output terminal coupled to an input terminal of a corresponding one of the OR gates, and a load enable terminal coupled to receive a load enable signal; and

a plurality of address decoders, each having a unique associated address, each of the address decoders having an output terminal coupled to a load input terminal of an input terminal of a corresponding one of the flip flops and to an input terminal of a corresponding one of the OR gates.

10. The FPGA of claim 9, wherein the exclusive OR gate coupled to the column select line associated with an initial column of CLBs has an input terminal coupled to receive a logic signal having a predetermined state.

11. The FPGA of claim 9, wherein the row select circuit comprises:

a plurality of cascaded exclusive OR gates, wherein each of the exclusive OR gates of the row select circuit has an output terminal which is coupled to a corresponding row select line;

a plurality of OR gates, wherein each of the OR gates has an output terminal coupled to an input terminal of a corresponding one of the exclusive OR gates of the row select circuit;

a plurality of flip flops, wherein each of the flip flops has an output terminal coupled to an input terminal of a corresponding one of the OR gates of the row select circuit, and a load enable terminal coupled to receive a load enable signal; and

a plurality of address decoders, each having a unique associated address, each of the address decoders having an output terminal coupled to a load input terminal of an input terminal of a corresponding one of the flip flops of the row select circuit and to an input terminal of a corresponding one of the OR gates of the row select circuit.

12. The FPGA of claim 11, wherein the exclusive OR gate coupled to the row select line associated with an initial row of CLBs has an input terminal coupled to receive a logic signal having a predetermined state.

13. A field programmable gate array (FPGA) comprising:

an array of configurable logic blocks (CLBs) arranged in a plurality of rows and columns, wherein each of the CLBs includes a reconfiguration circuit for reconfiguring the CLB, and an enabling circuit for enabling the reconfiguration circuit;

a plurality of column select lines, wherein each of the column select lines is coupled to each of the enabling circuits in a corresponding column of the CLBs;

a plurality of row select lines, wherein each of the row select lines is coupled to each of the enabling circuits in a corresponding row of the CLBs;

a column select circuit coupled to each of the column select lines, wherein the column select circuit comprises a plurality of cascaded multiplexers, wherein each of the multiplexers has an output terminal which is coupled to a corresponding column select line, wherein the column select circuit is controlled to assert column select signals on one or more consecutive column select lines; and

a row select circuit coupled to each of the row select lines, wherein the row select circuit is controlled to assert row select signals on one or more consecutive row select lines, wherein the enabling circuits that receive both a column select signal and a row select signal enable the associated reconfiguration circuits.

14. The FPGA of claim 13, wherein the row select circuit comprises a plurality of cascaded multiplexers, wherein each of the multiplexers of the row select circuit has an output terminal which is coupled to a corresponding row select line.

15. The FPGA of claim 13, wherein the column select circuit further comprises:

a plurality of flip flops, each flip flop having an output terminal coupled to a first control terminal of a corresponding one of the multiplexers, each flip flop further having a load enable terminal coupled to receive a load enable signal; and

a plurality of address decoders, each having a unique address and being coupled to receive an address signal, wherein each of the address decoders has an output terminal coupled to in input terminal of a corresponding one of the flip flops and to a second control terminal of a corresponding one of the multiplexers.

16. The FPGA of claim 15, wherein each of the multiplexers further comprises a first input terminal coupled to receive a input signal having a first logic state and a second input terminal coupled to receive an input signal having a second logic state.

17. The FPGA of claim 16, wherein a multiplexer associated with a first column of the array of CLBs is further coupled to receive an input signal having the second logic state.

18. A field programmable gate array (FPGA) comprising:

an array of configurable logic blocks (CLBs) arranged in a plurality of rows and columns, wherein each of the CLBs includes a reconfiguration circuit for reconfiguring the CLB, and an enabling circuit for enabling the reconfiguration circuit;

a plurality of column select lines, wherein each of the column select lines is coupled to each of the enabling circuits in a corresponding column of the CLBs;

a plurality of row select lines, wherein each of the row select lines is coupled to each of the enabling circuits in a corresponding row of the CLBs;

a column select circuit comprising a first plurality of logic gates having binary outputs, each of the logic gates having an output terminal coupled to a corresponding column select line, wherein the column select circuit is controlled to assert column select signals on one or more consecutive column select lines; and

a row select circuit comprising a second plurality of logic gates having binary outputs, each of the logic gates having an output terminal coupled to a corresponding row select line, wherein the row select circuit is controlled to assert row select signals on one or more consecutive row select lines, wherein the enabling circuits that receive both a column select signal and a row select signal enable the associated reconfiguration circuits, and wherein the first plurality of logic gates comprises a plurality of cascaded exclusive OR gates.

19. The FPGA of claim 18, wherein the second plurality of logic gates comprises a plurality of cascaded exclusive OR gates.