Ferroelectric memory and screening method therefor

• US 6,046,926 A
• Filed: 10/13/1998
• Issued: 04/04/2000
• Est. Priority Date: 10/15/1997
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Takenaka, Hiroyuki, Tanaka, Sumio, Shimizu, Mitsuru
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): LE, THONG QUOC
• Application Number:
  US09/170,104
• Time in Patent Office: 539 Days
• Field of Search: 365/145, 365/65, 365/149, 365/230.03, 365/230.06, 365/201
• US Class Current: 365/145
• CPC Class Codes: G11C 29/34 Accessing multiple bits simultaneously

Abstract

A ferroelectric memory has a memory cell screening test circuit connected to bit lines through switching transistors. In screening, at least one word line is selected, and data is simultaneously written in all memory cells connected to this word line. Since data is not restored after the rewrite, all FRAM cells can be screened under the same condition. By this circuit, a memory cell having a write failure according to the imprint characteristics inherent to the ferroelectric memory is screened.

Claims

1. A ferroelectric memory comprising:

a memory cell array in which a plurality of memory cells are arrayed in rows and columns, each of the plurality of memory cells including an information storage capacitor and a first MOS transistor, which is connected to the information storage capacitor in series, the information storage capacitor having a first and a second electrode opposing each other and a ferroelectric film sandwiched by the first and the second electrode, the first MOS transistor having first source and drain regions and a first gate electrode, and one of the first source and drain regions being connected to the first electrode of the capacitor;

a plurality of word lines arrayed in correspondence with the rows, each of the plurality of word lines being connected to the first gate electrode of the first MOS transistor of each of the plurality of memory cells arrayed on a corresponding one of the rows;

a row decoder for selectively driving the plurality of word lines;

a plurality of plate lines, each of the plate lines being connected to the second electrode of the capacitor of each of the plurality of memory cells arrayed on a corresponding one of the rows;

a plurality of bit lines arrayed in correspondence with the columns and arranged to cross the plurality of word lines, each of the plurality of bit lines being connected to the other of the first source and drain regions of the first MOS transistor of each of the plurality of memory cells arrayed on a corresponding one of the columns;

a plurality of second MOS transistors for bit line selection, which are coupled to the plurality of bit lines, respectively, each of the second MOS transistors having second source and drain regions and a second gate electrode, and one of the second source and drain regions being connected to a corresponding one of the plurality of bit lines; and

a test circuit connected to the second gate electrode of each of the plurality of second MOS transistors, the test circuit transferring data to the plurality of memory cells through the plurality of bit lines and the plurality of second MOS transistors.

2. The ferroelectric memory according to claim 1, wherein the test circuit for screening the plurality of memory cells comprises

a third p-channel type MOS transistor having third source and drain regions, a third gate electrode, and a backgate electrode,

a fourth n-channel type MOS transistor having fourth source and drain regions and a fourth gate electrode, and

a first and a second external input terminal,

one of the third source and drain regions and the backgate electrode are connected to the first external input terminal, the third gate electrode is connected to the second external input terminal, and the other of the third source and drain regions is connected to the second gate electrode of each of the plurality of second transistors,

one of the fourth source and drain regions is connected to a ground potential, the fourth electrode is connected to the second external input terminal, and the other of the fourth source and drain regions is connected to the second gate electrode of each of the plurality of second transistors, and

the plurality of bit lines form a plurality of bit line pairs each comprising a bit line and a complementary bit line, the bit line and the complementary bit line being connected to a third and a fourth external input terminal for test through corresponding ones of the plurality of second transistors for bit line selection, respectively.

3. The ferroelectric memory according to claim 2, wherein a plurality of corresponding plate lines of the plurality of plate lines are arranged for each of the plurality of word lines.

4. The ferroelectric memory according to claim 3, further comprising a plate line decoder having operation of decoding a selection signal for the row decoder and a column address and selectively driving one of the plurality of corresponding plate lines.

5. The ferroelectric memory according to claim 2, wherein the memory cell array is divided into a plurality of blocks, each of the plurality of blocks having the row decoder to selectively drive the plurality of word lines.

6. The ferroelectric memory according to claim 5, wherein a plurality of corresponding plate lines of the plurality of plate lines are arranged for each of the plurality of word lines contained in each of the plurality of blocks.

7. The ferroelectric memory according to claim 6, further comprising a plate line decoder for each of the blocks, the plate line decoder having operation of decoding a selection signal for the row decoder for each of the blocks and a column address to selectively drive one of the plurality of plate lines.

8. The ferroelectric memory according to claim 2, further comprising a sense amplifier and a column selection gate connected to each of the plurality of bit line pairs, and a test mode selection circuit connected to the first external input terminal of the test circuit, the test mode selection circuit having operation of stopping functions of the sense amplifier and the column selection gate in a test mode.

9. The ferroelectric memory according to claim 2, wherein the row decoder is divided into a plurality of row decoder blocks, and the memory further comprises a row decoder block selection circuit for selectively driving the plurality of row decoder blocks.

10. The ferroelectric memory according to claim 9, wherein the row decoder selection circuit has operation of selecting all of the plurality of row decoder blocks in the test mode.

11. A method of screening the ferroelectric memory of claim 2, comprising the steps of:

supplying signals to the first and the second external input terminal of the test circuit to drive the test circuit;

applying signals of opposite levels to the third and the fourth external input terminal, respectively;

selecting at least one of the plurality of word lines; and

writing data in the plurality of memory cells connected to the at least one of the plurality of word lines in accordance with a test mode external input signal.

12. A method according to claim 11, wherein the step of selecting at least one of the plurality of word lines comprises the step of selecting all of the plurality of word lines.

13. A method of screening said ferroelectric memory of claim 5, comprising the steps of:

supplying signals to the first and the second external input terminal of the test circuit to drive the test circuit;

applying signals of opposite levels to the third and the fourth external input terminal, respectively;

selecting at least one of the plurality of word lines in units of the plurality of memory cell array blocks; and

writing data in the plurality of memory cells connected to the at least one of the plurality of word lines in accordance with a test mode external input signal.

14. A method of screening said ferroelectric memory of claim 8, comprising the steps of:

supplying signals to the first and the second external input terminal of said test circuit to drive the test circuit;

applying signals of opposite levels to the third and the fourth external input terminal, respectively;

selecting at least one of the plurality of word lines;

stopping the sense amplifier circuit and the column selection gate in accordance with a test mode external input signal; and

writing data in the plurality of memory cells connected to the at least one of the plurality of word lines in accordance with the test mode external input signal.

15. A ferroelectric memory comprising:

a plurality of memory cells, each of the memory cells having a first transistor and a ferroelectric capacitor, the ferroelectric capacitor having a first electrode, a second electrode and a ferroelectric film interposed between the first and the second electrode, each of the first transistor having a first gate electrode and a first current path, one end of the first current path being connected to the first electrode of the ferroelectric capacitor;

a plurality of bit lines, each connected to the other end of the first current path of the first transistor in a corresponding one of the plurality of memory cells;

a plurality of word lines, each connected to the first gate electrode of the first transistor in a corresponding one of the plurality of memory cells;

a plurality of second transistors, each having a second gate electrode and a second current path, one end of the second current path being connected to a corresponding one of the plurality of bit lines;

a test circuit connected to the second gate electrode of each of the plurality of second transistors, the test circuit selecting the plurality of second transistors in a test mode; and

a pad receiving data and transferring the data to a corresponding one of the plurality of memory cells through a corresponding one of the plurality of second transistors and a corresponding one of the plurality of bit lines.

16. A ferroelectric memory comprising:

a plurality of memory cells, each of the memory cells having a first transistor and a ferroelectric capacitor, the ferroelectric capacitor having a first electrode, a second electrode and a ferroelectric film interposed between the first and the second electrode, each of the first transistor having a first gate electrode and a first current path, one end of the first current path being connected to the first electrode of the ferroelectric capacitor;

a plurality of bit lines, each connected to the other end of the first current path of the first transistor in a corresponding one of the plurality of memory cells;

a plurality of word lines, each connected to the first gate electrode of the first transistor in a corresponding one of the plurality of memory cells;

a plurality of second transistors, each having a second gate electrode and a second current path, one end of the second current path being connected to a corresponding one of the plurality of bit lines;

a first pad supplied with a predetermined voltage;

a test circuit connected to the second gate electrode of each of the plurality of second transistors, the test circuit having an inverter circuit formed of a p-channel type MOS transistor and an n-channel type MOS transistor, the p-channel MOS transistor having a source terminal and a drain terminal, the source terminal being supplied with the predetermined voltage applied to the first pad; and

a second pad receiving data and transferring the data to a corresponding one of the plurality of memory cells through a corresponding one of the plurality of second transistors and a corresponding one of the plurality of bit lines.

17. The ferroelectric memory according to claim 16, wherein the test circuit selects the plurality of second transistors in a test mode.

18. The ferroelectric memory according to claim 16, wherein the first pad is supplied with the predetermined voltage in a test mode.

19. A ferroelectric memory comprising:

a plurality of memory cells, each of the memory cells having a first transistor and a ferroelectric capacitor, the ferroelectric capacitor having a first electrode, a second electrode and a ferroelectric film interposed between the first and the second electrode, each of the first transistor having a first gate electrode and a first current path, one end of the first current path being connected to the first electrode of the ferroelectric capacitor;

a plurality of bit lines, each connected to the other end of the first current path of the first transistor in a corresponding one of the plurality of memory cells;

a plurality of word lines, each connected to the first gate electrode of the first transistor in a corresponding one of the plurality of memory cells;

a plurality of second transistors, each having a second gate electrode and a second current path, one end of the second current path being connected to a corresponding one of the plurality of bit lines;

a first pad supplied with a predetermined voltage;

a second pad supplied with a predetermined signal;

a signal line connected to the second gate electrode of each of the plurality of second transistors;

a test circuit having an inverter, the inverter having an input terminal, an output terminal and a power supply terminal, the power supply terminal being supplied with the predetermined voltage applied to the first pad, the output terminal of the inverter being connected to the signal line, the input terminal of the inverter circuit being supplied with the predetermined signal applied to the second pad; and

a third pad receiving data and transferring the data to a corresponding one of the plurality of memory cells through a corresponding one of the plurality of second transistors and a corresponding one of the plurality of bit lines.

20. The ferroelectric memory according to claim 19, wherein the first pad is supplied with the predetermined voltage and the second pad is supplied with the predetermined signal in a test mode.