Circuit implementation to quench bit line leakage current in programming and over-erase correction modes in flash EEPROM

• US 6,046,932 A
• Filed: 10/13/1999
• Issued: 04/04/2000
• Est. Priority Date: 08/13/1999
• Status: Expired due to Term

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Bill, Colin, Haddad, Sameer S., Su, Jonathan Shi-Chang, Chan, Vei-Han
• Primary Examiner(s): Tran, Andrew Q.
• Application Number:
  US09/417,273
• Time in Patent Office: 174 Days
• Field of Search: 365/185.02, 365/185.12, 365/185.13, 365/185.3, 365/185.33
• US Class Current: 365/185.02
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 16/3404 Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
• CPC Class Codes: G11C 16/3409 Circuits or methods to recover overerased nonvolatile memory cells detected during erase verification, usually by means of a "soft" programming step

Abstract

A method of and a flash memory device for quenching bitline leakage current during programming and over-erase correction operations. The flash memory cells are organized in an array of I/O blocks with each block having columns and rows. An array of resistors is connected between the common array source connection and ground. The array of resistors is made up of sets of resistors, each set having a programming mode resistor and an APDE mode resistor. A data buffer switches either a programming mode resistor or APDE mode resistor into the circuit when a bitline is selected for either programming or APDE. The values of the resistors are selected to raise the voltage at the source above a selected threshold voltage of the memory cells so that over-erased cells will not provide leakage current to the bitline during either programming or APDE.

Claims

1. A semiconductor memory device, comprising:

flash memory cells organized in an array of n I/O blocks, each I/O block having m columns and p rows;

a drain of each flash memory cell in each column connected to a bitline;

a control gate of each flash memory cell in each row connected to a wordline;

a source of each flash memory cell in the array connected to a common array source connection;

each bitline in each of the n I/O blocks connected to a data buffer and logic circuitry device; and

a resistor array connected between the common array source connection and ground potential.

2. The semiconductor memory device of claim 1 wherein the resistor array comprises a set of resistors for each of the n I/O blocks.

3. The semiconductor memory device of claim 2 wherein the set of resistors for each of the n I/O blocks comprises:

a programming mode resistor and a programming mode switch; and

an (APDE) automatic programming disturb erase mode resistor and an APDE mode switch.

4. The semiconductor memory device of claim 3 further comprising:

a connection between the data buffer and logic circuitry device for each of the n I/O blocks and the programming mode switch for the corresponding I/O block; and

a connection between the data buffer and logic circuitry device for each of the n I/O blocks and the APDE switch for the corresponding I/O block.

5. The semiconductor memory device of claim 4 further comprising:

switching circuitry in each of the data buffer and logic circuitry devices to close the corresponding programming mode switch during programming of a memory cell in a bitline controlled by the data buffer and logic circuitry device; and

switching circuitry in each of the data buffer and logic circuitry devices to close the corresponding APDE mode switch during an APDE operation of a memory cell in a bitline controlled by the data buffer and logic circuitry device.

6. A method of quenching bitline leakage current in a semiconductor memory device in which the flash memory device comprises flash memory cells organized in an array of n I/O blocks, each I/O block having m columns and p rows, the method comprising:

connecting a drain of each flash memory cell in each column to a bitline;

connecting a control gate of each flash memory cell in each row to a wordline;

connecting a source of each flash memory cell in the array to a common array source connection;

connecting each bitline in each of the n I/O blocks to a data buffer and logic circuitry device; and

connecting a resistor array between the common array source connection and ground potential.

7. The method of claim 6 wherein connecting a resistor array between the common array source connection and ground potential is accomplished by connecting a set of resistors for each of the n I/O blocks between the common array source connection and ground potential.

8. The method of claim 7 wherein connecting a set of resistors for each of the n I/O blocks between the common array source connection and ground potential is accomplished by:

connecting a programming mode resistor and a programming mode switch between the common array source connection and ground potential; and

connecting an APDE mode resistor and an APDE mode switch between the common array source connection and ground potential.

9. The method of claim 8 further comprising:

connecting the data buffer and logic circuitry for each of the n I/O blocks to the programming mode switch for the corresponding I/O block; and

connecting the data buffer and logic circuitry for each of the n I/O blocks and the APDE mode switch.

10. The method of claim 9 further comprising:

providing switching circuitry in each of the data buffer and logic circuitry devices to close the corresponding programming mode switch during programming of a memory cell in a bitline controlled by the data buffer and logic circuitry device; and

providing switching circuitry in each of the data buffer and logic circuitry devices to close the corresponding APDE mode switch during an APDE operation of a memory cell in a bitline controlled by the data buffer and logic circuitry device.

11. The method of claim 10 further comprising closing the programming mode switches associated with I/O blocks in which memory cells are being programmed.

12. The method of claim 10 further comprising closing the APDE mode switches associated with I/O blocks in which memory cells are in an APDE mode.