Integrated circuit memory devices having direct access mode test capability and methods of testing same
First Claim
1. An integrated circuit memory device, comprising:
- a first memory array having a first plurality of data lines electrically coupled thereto;
a second memory array having a second plurality of data lines electrically coupled thereto;
a first plurality of latch units electrically coupled together in series as a first pipelined latch unit and electrically coupled in parallel to said first memory array by the first plurality of data lines;
a second plurality of latch units electrically coupled together in series as a second pipelined latch unit and electrically coupled in parallel to said second memory array by the second plurality of data lines; and
a test mode control circuit which electrically couples an output of the first pipelined latch unit to an input of the second pipelined latch unit, in response to a test mode control signal.
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Accused Products
Abstract
Integrated circuit memory devices include test mode control circuits to more efficiently route test data to a fewer number of output pins during test mode operation. The memory device may include first and second memory arrays having first and second pluralities of data lines electrically coupled thereto, respectively. First and second pluralities of latch units are also provided. The first plurality of latch units are electrically coupled together in series as a first pipelined latch unit and electrically coupled in parallel to the first memory array by the first plurality of data lines. The second plurality of latch units are electrically coupled together in series as a second pipelined latch unit and electrically coupled in parallel to the second memory array by the second plurality of data lines. A preferred test mode control circuit electrically couples an output of the first pipelined latch unit to an input of the second pipelined latch unit, in response to a test mode control signal (φDAE). This test mode control circuit enables the transfer of data from the first pipelined latch unit to the second pipelined latch unit during direct access test mode reading operations. This data can then be transferred from the first pipelined latch unit to an output driver and then serially transmitted to a single input/output pin. Additional memory arrays within the memory device may also be linked together during test mode operation to improve testing efficiency when multiple memory devices are tested simultaneously in a memory testing apparatus.
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Citations
27 Claims
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1. An integrated circuit memory device, comprising:
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a first memory array having a first plurality of data lines electrically coupled thereto; a second memory array having a second plurality of data lines electrically coupled thereto; a first plurality of latch units electrically coupled together in series as a first pipelined latch unit and electrically coupled in parallel to said first memory array by the first plurality of data lines; a second plurality of latch units electrically coupled together in series as a second pipelined latch unit and electrically coupled in parallel to said second memory array by the second plurality of data lines; and a test mode control circuit which electrically couples an output of the first pipelined latch unit to an input of the second pipelined latch unit, in response to a test mode control signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. An integrated circuit memory device, comprising:
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a first memory array having a first plurality of even and odd data lines electrically coupled thereto; a second memory array having a second plurality of even and odd data lines electrically coupled thereto; a first plurality of odd latch units electrically coupled together in series as a first odd pipelined latch unit and electrically coupled in parallel to said first memory array by the first plurality of odd data lines; a first plurality of even latch units electrically coupled together in series as a first even pipelined latch unit and electrically coupled in parallel to said first memory array by the first plurality of even data lines; a second plurality of odd latch units electrically coupled together in series as a second odd pipelined latch unit and electrically coupled in parallel to said second memory array by the second plurality of odd data lines; a second plurality of even latch units electrically coupled together in series as a second even pipelined latch unit and electrically coupled in parallel to said second memory array by the second plurality of even data lines; first test mode control circuit which electrically couples an output of the first odd pipelined latch unit to an input of the second odd pipelined latch unit, in response to a test mode control signal; and a second test mode control circuit which electrically couples an output of the first even pipelined latch unit to an input of the second even pipelined latch unit, in response to the test mode control signal. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26)
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27. A method of testing an integrated circuit memory device, comprising the steps of:
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transferring data in parallel from first and second memory arrays within the memory device to first and second pipelined latch units, respectively; and transferring data from the second pipelined latch unit to an output driver while simultaneously transferring data from the first pipelined latch unit into the second pipelined latch unit.
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Specification