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Integrated circuit memory devices having direct access mode test capability and methods of testing same

  • US 6,046,947 A
  • Filed: 11/24/1998
  • Issued: 04/04/2000
  • Est. Priority Date: 12/03/1997
  • Status: Expired due to Term
First Claim
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1. An integrated circuit memory device, comprising:

  • a first memory array having a first plurality of data lines electrically coupled thereto;

    a second memory array having a second plurality of data lines electrically coupled thereto;

    a first plurality of latch units electrically coupled together in series as a first pipelined latch unit and electrically coupled in parallel to said first memory array by the first plurality of data lines;

    a second plurality of latch units electrically coupled together in series as a second pipelined latch unit and electrically coupled in parallel to said second memory array by the second plurality of data lines; and

    a test mode control circuit which electrically couples an output of the first pipelined latch unit to an input of the second pipelined latch unit, in response to a test mode control signal.

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