Method and apparatus for automatic equalization of very high frequency multilevel and baseband codes using a high speed analog decision feedback equalizer

• US 6,047,026 A
• Filed: 09/30/1997
• Issued: 04/04/2000
• Est. Priority Date: 09/30/1997
• Status: Expired due to Fees

• Current Assignee: OHM Technologies International, LLC
• Original Assignee: OHM Technologies International, LLC
• Inventors: Hassen, Alarabi Omar, Iyer, Parameswaran Gopal, Chao, Emil Yu-Ming, Dagli, Nirav Pravinkumar
• Primary Examiner(s): Vo, Don N.
• Assistant Examiner(s): PHU, PHUONG M
• Application Number:
  US08/940,047
• Time in Patent Office: 917 Days
• Field of Search: 375/233, 375/236, 708/322, 708/323
• US Class Current: 375/233
• CPC Class Codes: H04L 2025/03363 Multilevel H04L2025/03369 takes precedence
• CPC Class Codes: H04L 2025/0349 as a feedback filter
• CPC Class Codes: H04L 25/03057 with a recursive structure H04L25/03031 takes precedence
• CPC Class Codes: H04L 25/061 providing hard decisions only; arrangements for tracking or suppressing unwanted low frequency components, e.g. removal of dc offset removal of dc offset in coupling arrangements H04L25/029, H04L25/0296

Abstract

A decision feedback equalizer circuit employing a current mode finite impulse response (FIR) filter. A decision feedback equalizer circuit comprises an attenuator block for scaling a received voltage signal, a first transconductor (voltage-to-current converter) for converting the received voltage signal to a current signal, a current mode finite impulse response (FIR) filter for adding or subtracting current increments from the current signal and generating an equalized current signal, a second transconductor (current-to-voltage converter) for converting the equalized current signal into an equalized voltage signal, a positive slicer block for determining when the equalized voltage signal achieves a positive threshold level, a negative slicer block for determining when the equalized voltage signal achieves a negative threshold level, and a plurality of delay lines coupled respectively to the slicer blocks and to the current mode FIR filter for providing tap enable signals to the current mode FIR filter in response to signals received from the slicers. The decision feedback equalizer circuit may further comprise a baseline wander correction block for providing a correction current to the current mode FIR filter to compensate for baseline wander in the input voltage signal, and an adaptation block for providing compensation signals to the current mode FIR filter to insure that the equalized voltage signal conforms to a predetermined format.

Claims

1. A decision feedback equalizer circuit comprising:

a voltage-to-current converter for receiving a voltage input signal and converting said voltage input signal to a current input signal;

a current mode finite impulse response filter coupled to said voltage-to-current converter for adding positive and negative current increments to said current input signal at selected times to produce an equalized current signal;

a positive slicer block coupled to said current mode finite impulse response filter for detecting when said equalized current signal achieves a positive threshold current level and, upon such detection, providing via a first delay line a plurality of negative tap enable signals at a plurality of predetermined delay times to said current mode finite impulse response filter;

a negative slicer block coupled to said current mode finite impulse response filter for detecting when said equalized current signal achieves a negative threshold current level and, upon such detection, providing via a second delay line a plurality of positive tap enable signals at a plurality of predetermined delay times to said current mode finite impulse response filter; and

a current-to-voltage converter coupled to said current mode finite impulse response filter for converting said equalized current signal to an equalized voltage signal.

2. The decision feedback equalizer circuit of claim 1 further comprising an attenuator circuit for scaling said voltage input signal prior to its receipt by said voltage-to-current converter.

3. The decision feedback equalizer circuit of claim 1 further comprising an adaptation circuit for activating and deactivating positive and negative tap enable signal generators such that said equalized voltage signal conforms to a proper configuration.

4. The decision feedback equalizer circuit of claim 1 further comprising a baseline wander correction circuit for providing a correction current to said current mode finite impulse response filter to compensate for baseline wander in said input voltage signal.

5. A decision feedback equalizer circuit for removing intersymbol interference from a received signal having pulse widths equal to or less than ten nanoseconds, said decision feedback equalizer circuit comprising:

means for converting said received signal to an input current signal;

means for adding positive and negative current increments to said input current signal to create an equalized current signal; and

means for converting said equalized current signal to an equalized voltage signal.

6. The decision feedback equalizer circuit of claim 5, wherein said means for adding and subtracting current increments from said input current signal comprises:

means for determining when said equalized voltage signal achieves positive and negative threshold values and for generating respective positive and negative indicator signals upon said detection;

means for generating, respectively, a programmably determinable number and sequence of enabling signals in response to said respective positive and negative indicator signals;

means for generating said positive and negative current increments in response to said enabling signals.

7. The decision feedback equalizer circuit of claim 6, wherein

said means for generating said positive and negative current increments comprises a current mode finite impulse response (FIR) filter;

said means for determining when said equalized voltage signal achieves positive and negative threshold values comprises a positive slicer circuit and a negative slicer circuit; and

said means for generating, respectively, a programmably determinable number and sequence of enabling signals comprises a plurality of delay line elements.

8. The decision feedback equalizer circuit of claim 7, wherein each said delay line element comprises a pair of symmetric push pull current starved inverters coupled to a third inverter with no current or delay control.

9. The decision feedback equalizer circuit of claim 7, wherein said positive and negative slicer circuits each comprise a first comparator circuit, a second comparator circuit, a SR latch circuit, a delay element and an AND gate,

said first and second comparator circuits each having an input for receiving said equalized voltage signal,

said first comparator circuit having a second input for receiving a maximum threshold voltage and an output coupled to a SET pad of said SR latch, said second;

said second comparator circuit having a second input for receiving a minimum threshold voltage and an output coupled to a first input of said AND gate,

said delay element having an input coupled to a Q output pad of said SR latch and having an output coupled to a second input of said AND gate; and

said AND gate having an output coupled to a RST pad of said SR latch.

10. The decision feedback equalizer circuit of claim 5 further comprising means for removing baseline wander from said equalized current signal.

11. A decision feedback equalizer circuit for removing intersymbol interference from a received signal having pulse widths less than or equal to ten nanoseconds, said decision feedback equalizer circuit comprising:

a first transconductor for converting said received signal to an input current signal;

a current mode finite impulse response filter network for adding positive and negative current increments to said input current signal to remove said intersymbol interference from said input current signal, thereby converting said input current signal to an equalized current signal; and

a second transconductor for converting said equalized current signal to an equalized voltage signal.

12. The decision feedback equalizer circuit of claim 11, wherein said finite impulse response filter network comprises:

a current mode finite impulse response filter including a plurality of quantized differential current sources for adding said positive and negative current increments to said input current signal;

a positive/negative slicer network for determining when said equalized voltage signal achieves predetermined positive and negative, maximum and minimum threshold levels and for generating indicator signals upon each such determination; and

a delay network coupled to said positive/negative slicer network and to said current mode finite impulse response filter for delivering a predetermined number and sequence of enabling signals to said quantized differential current sources of said current mode finite impulse response filter in response to receiving said indicator signals from said positive/negative slicer network.

13. The decision feedback equalizer circuit of claim 12, wherein said finite impulse response filter network further comprises a feedback network for eliminating baseline wander from said equalized current signal.

14. The decision feedback equalizer circuit of claim 12, wherein said finite impulse response filter network further comprises an attenuator circuit for scaling said received signal prior to a delivery of said received signal to said first transconductor.

15. A method for equalization of very high frequency multi-level and baseband codes, said method comprising:

providing an input voltage signal to a first transconductor to produce an input current signal;

providing said input current signal to a current mode finite impulse response filter, said current mode finite impulse response filter being configured to add positive and negative incremental currents to said input current in a programmably controllable manner to produce an equalized current signal; and

providing said equalized current signal to a second transconductor to produce an equalized voltage signal.

16. The method of claim 15 further comprising scaling said input voltage signal prior to providing said input voltage signal to said first transconductor.

17. The method of claim 15 further comprising:

detecting when said equalized current signal achieves positive and negative current threshold levels and

providing a plurality of delayed tap enable signals to said current mode finite impulse response filter in a programmably controlled sequence when said positive and negative current threshold levels are detected.

18. A method of filtering intersymbol interference in signal processing systems, said method comprising:

receiving an input voltage signal having pulse widths less than or equal to ten nanoseconds;

converting said input voltage signal to an input current signal;

adding positive and negative current increments to said input current signal to produce an equalized current signal; and

converting said equalized current signal to an equalized voltage signal.

19. The method of claim 18, wherein said adding positive and negative current increments to said input current signal is effected using a plurality of quantized differential current sources.

20. The method of claim 18, wherein said adding positive and negative current increments includes:

monitoring said equalized current signal to determine when said equalized current signal achieves positive and negative threshold levels; and

generating in response to said equalized current signal achieving said positive and negative threshold levels a plurality of tap enable signals for controlling the addition of said positive and negative current increments to said input current signal.

21. The method of claim 20, wherein a number of said tap enable signals generated in response to said equalized current signal achieving either a positive or a negative threshold is programmably variable, and wherein a period between said tap enable signals is programmably variable.

22. The method of claim 21, wherein said equalized voltage signal is monitored to determine whether said equalized voltage signal conforms to a predetermined signal definition, and wherein said number of tap enable signals is varied when said equalized voltage signal does not conform to said predetermined signal definition.

23. The method of claim 22, wherein said variation of said number of tap enable signals is performed by setting said number of tap enable signals to a predetermined maximum number and reducing said number of tap enable signals incrementally over a predetermined period of time until said equalized voltage signal conforms to said predetermined signal definition.