Method for configuring FPGA memory planes for virtual hardware computation

• US 6,047,115 A
• Filed: 05/29/1997
• Issued: 04/04/2000
• Est. Priority Date: 05/29/1997
• Status: Expired due to Term

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Trimberger, Stephen M., Mohan, Sundararajarao
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): Siek, Vuthe
• Application Number:
  US08/865,386
• Time in Patent Office: 1,041 Days
• Field of Search: 364/488, 364/489, 364/490, 395/500.17, 395/500.18, 712/22, 712/10, 712/11, 712/14, 712/15
• US Class Current: 716/117
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture

Abstract

A dynamically reconfigurable FPGA includes an array of tiles on a logic plane and a plurality of memory planes. Each tile has associated storage elements on each memory plane, called local memory. This local memory allows large amounts of data to pass from one FPGA configuration (memory plane) to another with no external memory access, thereby transferring data to/from the storage elements in the logic plane at very high speed. Typically, all the local memory can be simultaneously transferred to/from other memory planes in one cycle. Each FPGA configuration provides a virtual instruction. The present invention uses two different types of virtual instructions: computational and pattern manipulation instructions. Computational instructions perform some computation with data stored in some pre-defined local memory pattern. Pattern manipulation instructions move the local data into different memory locations to create the pattern required by the next instruction. A virtual computation may be accomplished by a sequence of instructions.

Claims

1. A method for computation in a programmable logic device (PLD), said PLD including a logic plane and a plurality of memory planes, said method comprising:

storing configuration data and user data in said memory planes, said configuration data providing a configuration of said PLD, and said configuration of said PLD using said user data providing a single instruction in said computation; and

sequentially reconfiguring said PLD in a series of configurations using said configuration data and user data, said series of configurations providing said computation,

wherein each computation is comprised of computation steps, each computation step receiving input data, generating output data, and using programmable routing of said PLD to provide output data from one computation step as input data for another computation step.

2. The method of claim 1 wherein said PLD comprises a plurality of memory planes, each memory plane storing user data and configuration data for a different configuration, wherein said method further comprises providing output data from one computation step for a first configuration defined by configuration data and user data on one memory plane as input data for another computation step for a second configuration defined by configuration data and user data on another memory plane.

3. The method of claim 2 wherein said output data is stored in said one memory plane in a first pattern and said input data is stored in said another memory plane in a second pattern.

4. A method of reconfiguring a dynamically reconfigurable programmable logic device (PLD), the PLD having a logic plane and a plurality of memory planes for modifying the functional characteristics of the PLD, the method comprising the steps of:

a) providing a first memory plane including configuration data and user data for the PLD, the user data being stored in the first memory plane in a first predetermined spatial pattern;

b) transferring the configuration data and the user data from the first memory plane to the logic plane;

c) configuring the PLD in accordance with the configuration data transferred from the first memory plane;

d) operating the PLD with the user data to generate new data; and

e) saving the new data to one or more of the memory planes in a second predetermined pattern.

5. The method recited in claim 4, wherein step e) is accomplished by using programmable wire routing on the PLD.

6. A method for carrying out a computation which includes a sequence of computation steps using a dynamically reconfigurable field programmable gate array (FPGA), the FPGA including a configurable logic plane and a plurality of memory planes, each memory plane including configuration data and user data, the user data being stored in a predetermined spatial pattern, the method comprising:

a) attributing to each computation step an instruction, the instruction including the configuration data and user data stored in at least one of the memory planes;

b) transferring the configuration data and the user data in step a) to the logic plane, the user data being arranged in a first predetermined spatial pattern;

c) configuring the FPGA in accordance with the configuration data;

d) operating the FPGA with the user data to produce new user data;

e) saving the new user data to one or more of the memory planes in a second predetermined spatial pattern; and

f) sequentially repeating steps b) through e) in accordance with the instructions stored in the memory planes to sequentially perform the computation steps.

7. The method recited in claim 6 wherein each computation step requires input user data and the performance of each computation step produces output user data, and wherein the output user data of one computation step is used as the input user data of a subsequent computation step.

8. The method recited in claim 7, wherein the user data includes the input user data and the new user data includes the output user data.

9. A method for performing a virtual hardware computation in a programmable logic device (PLD), the PLD including a logic plane and a plurality of memory planes, the method comprising the steps of:

determining the required steps of a computation task;

for each required step, assigning a functional specification of a corresponding virtual instruction;

browsing a virtual instruction library for the required virtual instructions;

for each required step for which there is no virtual instruction in the virtual instruction library, if any, using the assigned functional specification and a timing specification to design new configuration data for the PLD to accomplish that step and thereby produce a new required virtual instruction;

collecting and assembling all of the required virtual instructions as a sequence of virtual instructions, and wherein each virtual instruction is stored as configuration data and predefined input and output patterns of user data, the input pattern being before the instruction is carried out and the output pattern being after the instruction is carried out;

determining whether the output pattern of one instruction matches the input pattern of a next consecutive instruction; and

inserting a pattern manipulation instruction in the sequence of virtual instructions whenever the output pattern of one virtual instruction does not match the input pattern of the next consecutive virtual instruction.