Method of estimating degradation with consideration of hot carrier effects
First Claim
1. A hot-carrier-delay-degradation estimation method of estimating, in timing verification of an LSI designed on a cell level, deterioration in reliability of the LSI due to the influence of hot carriers, comprising the steps of:
- a delay calculation step of calculating, for cells forming an LSI serving as an object of timing verification, delays, signal slew at input terminals of said cells, and load capacitances connected to output terminals of said cells, the calculations being based on (i) circuit information comprising characteristic information of said cells, information of connection between said cells and cell-to-cell wirings, and characteristic information of said cell-to-cell wirings, and (ii) a delay library containing delay parameters to be used for calculating said delays; and
a delay degradation library generation step of generating a delay degradation library by obtaining delay parameters of said cells at the time when said LSI has operated for a predetermined period of time, and then generating said delay degradation library containing said delay parameters thus obtained, said delay parameters being obtained (i) based on said delay library and on delay degradation parameters, in which changes in delay of each of said cells due to the influence of hot carriers are expressed in terms of changes in delay parameters accompanied by a number of operation times of each of said cells, and (ii) with the use of an estimated number of operation times of each of said cells at the time when said LSI has operated for said predetermined period of time, and of said input signal slew and output load capacitances of said cells calculated in said delay calculation step,said delay calculation step and said delay degradation library generation step being repeated a predetermined number of repetition times,wherein on and after the second repetition time, said delay calculation step and said delay degradation library generation step being executed using, instead of said delay library, the delay degradation library generated at the delay degradation library generation step which has been just previously executed prior to a current repetition time,whereby deterioration in reliability of said LSI due to the influence of hot carriers is estimated based on the delays of said cells calculated at the delay calculation step which has been lastly executed.
1 Assignment
0 Petitions
Accused Products
Abstract
There is provided a hot-carrier-delay-degradation estimation method of estimating, based on the actual operation of an LSI, deterioration in reliability thereof due to the influence of hot carriers. At a delay calculation step, there are calculated, for the cells of an LSI serving as the object of timing verification, delays, input slew and output load capacitances based on circuit information and a delay library containing delay parameters. At a delay degradation library generation step, there is generated a delay degradation library containing delay parameters at the time when the LSI has operated for a predetermined period of time. This delay degradation library is generated (i) based on the delay library and delay degradation parameters in which changes in delay of the cells due to the influence of hot carriers are expressed in terms of changes in delay parameter accompanied by the numbers of operation times of the cells and (ii) with the use of the estimated numbers of operation times, input waveform inclinations and output load capacitances of the cells. By repeating these two steps the predetermined number of repetition times, there are obtained delays of the cells at the time when the LSI has operated for a period of time equivalent to the product of the predetermined period of time and the number of repetition times.
-
Citations
9 Claims
-
1. A hot-carrier-delay-degradation estimation method of estimating, in timing verification of an LSI designed on a cell level, deterioration in reliability of the LSI due to the influence of hot carriers, comprising the steps of:
-
a delay calculation step of calculating, for cells forming an LSI serving as an object of timing verification, delays, signal slew at input terminals of said cells, and load capacitances connected to output terminals of said cells, the calculations being based on (i) circuit information comprising characteristic information of said cells, information of connection between said cells and cell-to-cell wirings, and characteristic information of said cell-to-cell wirings, and (ii) a delay library containing delay parameters to be used for calculating said delays; and a delay degradation library generation step of generating a delay degradation library by obtaining delay parameters of said cells at the time when said LSI has operated for a predetermined period of time, and then generating said delay degradation library containing said delay parameters thus obtained, said delay parameters being obtained (i) based on said delay library and on delay degradation parameters, in which changes in delay of each of said cells due to the influence of hot carriers are expressed in terms of changes in delay parameters accompanied by a number of operation times of each of said cells, and (ii) with the use of an estimated number of operation times of each of said cells at the time when said LSI has operated for said predetermined period of time, and of said input signal slew and output load capacitances of said cells calculated in said delay calculation step, said delay calculation step and said delay degradation library generation step being repeated a predetermined number of repetition times, wherein on and after the second repetition time, said delay calculation step and said delay degradation library generation step being executed using, instead of said delay library, the delay degradation library generated at the delay degradation library generation step which has been just previously executed prior to a current repetition time, whereby deterioration in reliability of said LSI due to the influence of hot carriers is estimated based on the delays of said cells calculated at the delay calculation step which has been lastly executed. - View Dependent Claims (2, 3, 4, 5, 6)
-
-
7. A hot-carrier-delay-degradation estimation method of estimating, in timing verification of an LSI designed on a cell level, deterioration in reliability of the LSI due to the influence of hot carriers, comprising the steps of:
-
a step of previously preparing, for cells forming an LSI serving as an object of timing verification, a delay library group comprising a plurality of delay libraries which contain delay parameters to be used for calculating delays of said cells at the time when said cells have operated a predetermined number of operation times, and which are different in a number of cell operation times from one another; a delay degradation library generation step (i) at which, based on said delay library group and an estimated number of operation times of each of said cells at the time when said LSI has operated for a predetermined period of time, there are obtained, for each of said cells, delay parameters at the time when each of said cells have operated respectively said estimated number of operation times and (ii) at which there is generated a delay degradation library containing said delay parameters thus obtained; and a delay calculation step of calculating delays of said cells based on said delay degradation library, circuit information comprising characteristic information of said cells, information of connection between said cells and cell to-cell wirings, and characteristic information of said cell-to-cell wirings, whereby deterioration in reliability of said LSI due to the influence of hot carriers is estimated based on said delays of said cells calculated at said delay calculation step. - View Dependent Claims (8)
-
-
9. A hot-carrier-delay-degradation estimation method of estimating, in timing verification of an LSI designed on a cell level, deterioration in reliability of the LSI due to the influence of hot carriers, comprising:
-
a delay calculation step of calculating, for cells forming an LSI serving as an object of timing verification, delays, signal slew at the input terminals and load capacitances connected to the output terminals, such calculation being made based on (i) circuit information comprising characteristic information of said cells, information of connection between said cells and the cell-to-cell wirings, and characteristic information of said cell-to-cell wirings, and (ii) a delay library containing delay parameters to be used for calculation of cell delays; a delay degradation amount calculation step of calculating amounts of delay degradation, of said cells at the time when said LSI has operated for a predetermined period of time, such calculation being made (i) based on delay degradation parameters in which changes in delay of each of said cells due to the influence of hot carriers are expressed in terms of changes in delay parameters accompanied by a number of operation times of each of said cells, and (ii) with the use of an estimated number of operation times of each of said cells at the time when said LSI has operated for said predetermined period of time, and of the input slew and output load capacitances of said cells calculated at said delay calculation step; and an after-deterioration delay calculation step of calculating delays of said cells by adding the delays calculated at said delay calculation step to said amounts of delay degradation calculated at said delay degradation amount calculation step, whereby deterioration in reliability of said LSI due to the influence of hot carriers is estimated based on said delays of said cells calculated at said after-deterioration delay calculation step.
-
Specification