Method and apparatus for performing lane arithmetic to perform network processing
First Claim
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1. A method of calculating a sum in a processor, said method comprising:
- storing a data set as a sequential series of data values in a memory, the data values being associated with lanes of data values of a selectable bit width;
sequentially adding a subset of said sequential series of data values to contents of a register using lane arithmetic to generate a sequence of partial sums within the register, the subset of said sequential series of data values are selected such that lanes of data values within the subset of said sequential series of data values are aligned and added within lanes of the register; and
executing bit field arithmetic operations on the contents of the resister within the lanes in order to reduce said sequence of partial sums into a final sum within a lane of the register.
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Abstract
A method and apparatus for processing network packets is disclosed. A Single Instruction Multiple Data (SIMD) architecture processor is disclosed. The SIMD processor includes several instructions designed specifically for the task of network packet processing. For example, SIMD add instructions for performing one'"'"'s complement additions are included to quickly calculate Internet checksums. Furthermore, the SIMD processor includes several instructions for performing lane arithmetic.
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Citations
25 Claims
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1. A method of calculating a sum in a processor, said method comprising:
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storing a data set as a sequential series of data values in a memory, the data values being associated with lanes of data values of a selectable bit width; sequentially adding a subset of said sequential series of data values to contents of a register using lane arithmetic to generate a sequence of partial sums within the register, the subset of said sequential series of data values are selected such that lanes of data values within the subset of said sequential series of data values are aligned and added within lanes of the register; and executing bit field arithmetic operations on the contents of the resister within the lanes in order to reduce said sequence of partial sums into a final sum within a lane of the register. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. An apparatus for processing sequential instructions, said apparatus comprising:
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a register for storing bits of data; an instruction execution unit, said instruction execution unit including logic to receive lane arithmetic instructions and control the execution thereof; and an arithmetic logic unit, said arithmetic logic unit having logic to execute lane arithmetic instructions on lanes within said register, a lane being a range of bits as specified by a lane arithmetic instruction. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18)
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19. A method of verifying that a packet of data was correctly received by a network device in a network, the packet of data including a transmitted checksum and a plurality of data words each being a lane wide of a predetermined number of bits forming a plurality of lanes, the method comprising:
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arranging the data words into a sequence of data words, the sequence of data words formed by placing lanes of data words end to end in alignment for addition in parallel together; adding each parallel lane of the sequence of data words together using lane arithmetic resulting in a partial sum in each lane; adding each partial sum together using bit field arithmetic to form a final sum representative of a calculated checksum; and comparing the final sum with the transmitted checksum to determine if the packet was correctly received. - View Dependent Claims (20, 21)
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22. A network device having a single instruction multiple data (SIMD) processor, the network device using the SIMD processor and a received checksum to verify the correct receipt of data packets across the network, each data packet including a plurality of data values each data value being a lane wide and each lane being a plurality of bits wide, the network device comprising:
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the SIMD processor including an arithmetic logic unit and a register having a width of N lanes, the arithmetic logic unit to perform lane arithmetic or bit field arithmetic in response to a single instruction, the register to couple to the arithmetic logic unit during execution of instructions and storing the operands and the results thereof; a processor readable storage medium; and a processor readable code recorded in the processor readable storage medium to load N data values into the N respective lanes of the register as an operand, add the next N data values in parallel to the contents within the N lanes of the register using lane arithmetic to form a partial sum in lanes of the register, add at least one lane of contents within the register to another at least one lane of contents in the register using bit field arithmetic to reduce the partial sum in lanes of the register to a final sum in a lane of the register, the final sum representative of a calculated checksum, and compare the final sum with the received checksum to verify that the data packet was correctly received. - View Dependent Claims (23, 24, 25)
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Specification