Parasitic personal computer interface

• US 6,047,337 A
• Filed: 06/16/1997
• Issued: 04/04/2000
• Est. Priority Date: 08/09/1995
• Status: Expired due to Fees

• Current Assignee: Cirrus Logic Incorporated
• Original Assignee: Cirrus Logic Incorporated
• Inventors: Smith, Wesley H.
• Primary Examiner(s): Dinh, Dung C.
• Application Number:
  US08/876,776
• Time in Patent Office: 1,023 Days
• Field of Search: 395/800.34, 395/800.35, 395/200.46, 395/200.42, 395/200.43, 395/842, 395/847, 395/825, 395/892, 395/500, 395/309, 395/311, 395/200.38 , 395/200.41, 395/843, 711/147, 711/150, 711/153, 712/35
• US Class Current: 710/23
• CPC Class Codes: G06F 13/126 and has means for transferring I/O instructions and statuses between control unit and main processor
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices

Abstract

A method and apparatus for coupling an External Device to a Host Computer, such that program code to be executed by the external device may be stored in the Host Computer memory and yet be essentially independent of the Host Computer. Hardware and software enable the logical displacement of a program and address bus across inter-processor interfaces. An External Device preferably provides direct access to program code stored within Host Computer memory by means of a conventional DMA function. Program code which is to be executed by the External Processor within the External Device is transferred from the Host Memory to an Instruction Buffer memory within the External Device. The External Processor determines when to request additional instructions from the Host Memory over the DMA channel on a timed interrupt basis. The External Processor requires an instruction that is not present in the buffer, then the buffer returns an instruction to the External Processor that causes the External Processor to request additional instructions from the Host Memory which include the required instruction. A multiplexer is provided which allows instructions to be provided to the External Processor from a special purpose program memory in which instructions for special purpose functions are stored. Functions within the program code stored within the Host Memory (i.e., "CP" functions) are preferably not time critical functions. Accordingly, the program code that is stored in the Host Memory and which is to be executed by a processor within the External Device is referred to as a "CP Function Program Code". Time critical functions to be performed by the processors of the External Device are preferably not performed by the CP Function Program Code, but rather are performed by executing program code that is stored locally (i.e.,"External Program Code).

Claims

1. An external device for use with a host computer having a host memory for storing program and data for use by the host computer, including:

(a) a means for requesting a direct memory access, coupled to the host memory, for initiating a direct memory access operation in order to access information, including program instructions, stored within the host memory;

(b) a secondary computer, coupled to the direct memory access controller, for transmitting and receiving information from the direct memory access controller, including program instructions to be executed by the secondary computer;

further including;

(c) a special function program memory, coupled to the secondary computer, for storing special function programs; and

(d) a multiplexer, coupled to the secondary computer, the special function program memory, and the direct access memory device, for selectively coupling instructions to the secondary computer from either the direct memory access device or the local special function program memory, further including an instruction buffer, coupled to the host memory and to the direct memory access device, for buffering instructions received from the host memory, and making the received instructions available to the secondary computer.

2. A modem, for communicating between a first and second end station, the first end station having a general purpose host computer having a host memory, said modem including:

a direct memory access controller for accessing information stored within the host memory;

a digital signal processor coupled to the direct memory access controller effective for causing the direct memory access controller to initiate a direct memory access operation in response to requirements derived internally to the digital signal processor in order to make program instructions available to the digital signal processor and for receiving from the direct memory access controller program instructions read by the direct memory access controller from the host memory to be executed by the digital signal processor;

wherein the program instructions control the operation of the digital signal processor to demodulate the information to be communicated between the first and second end stations.