System for adjusting slew rate on an output of a drive circuit by enabling a plurality of pre-drivers and a plurality of output drivers

• US 6,047,346 A
• Filed: 02/02/1998
• Issued: 04/04/2000
• Est. Priority Date: 02/02/1998
• Status: Expired due to Term

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Wei, Jason, Patel, Samir A., Lau, Benedict C., Chan, Yiu-Fai, Ho, Tsyr-Chyang
• Primary Examiner(s): Lee, Thomas C.
• Assistant Examiner(s): ELAMIN, ABDELMONIEM I
• Application Number:
  US09/017,529
• Time in Patent Office: 792 Days
• Field of Search: 710/126, 710/8, 327/158, 327/170, 327/262, 327/374, 327/380, 361/18
• US Class Current: 327/158
• CPC Class Codes: G06F 13/4072 Drivers or receivers G06F13/4086 takes precedence; for multistate logic circuits H03K19/0002

Abstract

An interface circuit providing a high speed bus. According to one embodiment, the interface circuitry includes a plurality of I/O pins coupled to a plurality of bus drivers, wherein each bus driver is configured to adjust the rise time, fall time, and drive strength of outputs signal on the I/O pins based on process-voltage-temperature ("PVT") conditions. The circuitry used to adjust the I/O outputs includes a slew rate control circuit, a current control circuit, and a delay lock loop ("DLL").

Claims

1. A drive circuit, comprising:

a plurality of selector circuits;

a plurality of control inputs;

a plurality of pre-driver groups having a plurality of pre-drivers, each pre-driver group coupled to a corresponding one of the plurality of selector circuits, each pre-driver group coupled to the plurality of control inputs, the control inputs to enable one or more of the plurality of pre-drivers within each pre-driver group; and

a plurality of output drivers, each output driver having an input and an output, each input of an output driver coupled to a corresponding one of the plurality of pre-driver groups, the selector circuits to enable one or more of the plurality of output drivers, the outputs of the plurality of output drivers coupled together and having a slew rate, the slew rate determined by a first number of the plurality of pre-drivers that are enabled and by a second number of the plurality of output drivers that are enabled.

2. The drive circuit of claim 1, wherein varying the first number of pre-drivers and the second number of output drivers changes the slew rate.

3. The drive circuit of claim 2, wherein the plurality of control inputs determines the first number of pre-drivers within each pre-driver group that are coupled to the input of a corresponding one of the plurality of output drivers.

4. The drive circuit of claim 3, wherein increasing the first number of pre-drivers coupled to the input of a corresponding one of the plurality of output drives increases the slew rate.

5. The drive circuit of claim 1, wherein the plurality of selector circuits have data inputs and a clock input, the clock input to select from among the data inputs, the data inputs to enable one or more of the plurality of output drivers.

6. The drive circuit of claim 5, wherein the data inputs adjust the slew rate.

7. The drive circuit of claim 6, wherein the plurality of selector circuits comprise NAND gates coupled to multiplexers.

8. The drive circuit of claim 6, wherein the plurality of output drivers are NMOS transistors.

9. An interface circuit, comprising;

a plurality of drive circuits, each of the plurality of drive circuits having a first input, a second input, and an output;

a first control circuit coupled between the first input and the output of at least one of the plurality of drive circuits, the first control circuit to control a current flow on the output of the at least one of the plurality of drive circuits, the current flow based on an output voltage on the output of the at least one of the plurality of drive circuits; and

a second control circuit coupled to the second input of the at least one of the plurality of drive circuits, the second control circuit to control a slew rate on the output of the at least one of the plurality of drive circuits.

10. The interface circuit of claim 9, wherein the first control circuit comprises:

a voltage divider coupled to the output of the drive circuit to generate an internal voltage;

a comparator coupled to the voltage divider, the comparator to compare the internal voltage with a reference voltage, the comparator to generate a transition voltage; and

a counter coupled to receive the transition voltage from the comparator, the counter to incrementally adjust the current flow on the output of the drive circuit.

11. The interface circuit of claim 10, wherein the current flow is incrementally adjusted by selectively coupling a plurality of current sources to the output.

12. The interface circuit of claim 9, wherein the second control circuit comprises:

a logic circuit having a clock input and a trigger input, the logic circuit to generate a pulse signal having a pulse width based on the trigger input;

a one-shot circuit coupled to receive the pulse signal, the one-shot circuit to generate a plurality of control inputs, the control inputs to control the slew rate on the output of the at least one of the plurality of drive circuits.

13. The interface circuit of claim 12, wherein the trigger input is coupled to receive a calibration signal to initiate generation of the pulse signal propagated through the one-shot circuit.

14. The interface circuit of claim 9, wherein each of the plurality of drive circuits have a first and a second clock inputs and wherein the interface circuit further comprises:

a clock circuit coupled to the first and the second clock inputs, the clock circuit to synchronize two timing signals, the clock circuit to transmit the synchronized two timing signals to the first and the second clock inputs.

15. The interface circuit of claim 14, wherein the synchronized two timing signals have a predetermined relationship.

16. The interface circuit of claim 15, wherein the predetermined relationship is a 90 degree phase relationship.

17. The interface circuit of claim 16, wherein the clock circuit is a delay locked loop.

18. A data transfer system, comprising:

a bus having data lines, a first clock, and a second clock;

a first device and a second device coupled to the bus, each device having an interface circuit, the interface circuit further comprising;

a plurality of drive circuits, each of the plurality of drive circuits having a first input, a second input, a first clock input, a second clock input, and an output;

a clock circuit coupled to the first and the second clock inputs, the clock circuit to synchronize the first clock and the second clock, the clock circuit to transmit the synchronized first and second clocks to the first and the second clock inputs;

a first control circuit coupled between the first input and the output of at least one of the plurality of drive circuits, the first control circuit to control a current flow on the output of the at least one of the plurality of drive circuits; and

a second control circuit coupled to the second input of the at least one of the plurality of drive circuits, the second control circuit to control a slew rate on the output of the at least one of the plurality of drive circuits.

19. The data transfer system of claim 18, wherein the clock circuit operates to time data on the output of the plurality of driver circuits a phase prior to the first clock.

20. The data transfer system of claim 19, wherein the first device and the second device are memory devices.

21. A method of adjusting slew rate on an output of a drive circuit, comprising;

generating a plurality of drive control signals based on a calibration signal;

generating a current control signal based on a voltage of the output of the drive circuit; and

enabling a plurality of pre-drivers using the plurality of drive control signals, the plurality of pre-drivers coupled to a corresponding plurality of output drivers, the plurality of pre-drivers enabled to adjust the slew rate on the output of the drive circuit.

22. The method of claim 21, further comprising enabling at least one of a plurality of output drivers using on the current control signal.

23. The method of claim 22, further comprising generating a feedback loop to use the voltage of the output of the drive circuit to determine a drive current for the output.

24. The method of claim 21, further comprising timing a data output of the drive circuit to operate a phase prior to a first clock signal, the timing based on a synchronization of the first clock signal and a second clock signal.