Method of connecting a unit under test in a wireless test fixture

• US 6,047,469 A
• Filed: 11/12/1997
• Issued: 04/11/2000
• Est. Priority Date: 11/12/1997
• Status: Expired due to Fees

• Current Assignee: Luna Family Trust
• Original Assignee: Luna Family Trust
• Inventors: Luna, L. Jack
• Primary Examiner(s): Arbes, Carl J.
• Application Number:
  US08/968,960
• Time in Patent Office: 881 Days
• Field of Search: 29/825, 29/830, 29/833, 29/593, 324/754
• US Class Current: 29/830
• CPC Class Codes: G01R 1/0408 Test fixtures or contact fields; Connectors or connecting adaptors; Test clips; Test sockets G01R1/067 takes precedence; mass production testing systems G01R31/59; testing of connections G01R31/66; for testing printed circuit boards G01R31/2808
• CPC Class Codes: H05K 1/0287 having an universal lay-out, e.g. pad or land grid patterns or mesh patterns
• CPC Class Codes: H05K 1/0298 Multilayer circuits
• CPC Class Codes: H05K 2201/09454 Inner lands, i.e. lands around via or plated through-hole in internal layer of multilayer PCB
• CPC Class Codes: H05K 2201/0949 Pad close to a hole, not surrounding the hole if used for surface mounting H05K1/114
• CPC Class Codes: H05K 2201/09945 Universal aspects, e.g. universal inner layers or via grid, or anisotropic interposer
• CPC Class Codes: H05K 3/429 Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
• CPC Class Codes: Y10T 29/49126 Assembling bases
• CPC Class Codes: Y10T 29/49165 by forming conductive walled aperture in base

Abstract

A multilayer printed circuit board has prefabricated inner signal layers and unfinished top and bottom layers for customizing the board for a particular test installation. Each signal layer has a predetermined arrangement of circuits, each circuit having first and second via pads at opposite ends of the circuit. The first via pads form a virtual grid for selective connection to test points of a unit under test. The top layer is processed to provide a test pad aligned with each test point on a unit under test, a via pad for each test pad which is aligned with the closest available virtual grid via, and a connecting trace between each test pad and the associated via pad. Plated through holes are drilled through the board at each outer layer via pad for connection to the aligned virtual grid via. Similar processing of the bottom layer connects the via pad at the opposite end of each assigned inner layer circuit to an interface pad for connection to a respective terminal of automated test equipment.

Claims

1. A method of connecting a unit under test having a plurality of test points to automated test equipment, comprising the steps of:

providing a multi-layer printed circuit board for providing interconnections between test points on the unit under test and pre-selected terminals of automated test equipment, the printed circuit board having a plurality of stacked, pre-fabricated inner signal layers, each signal layer having a predetermined arrangement of spaced circuits each having a first via pad at one end and a second via pad at the opposite end, the first via pads forming a virtual grid of vias for selective connection to test points of a unit under test, and first and second outer layers secured at opposite ends of the stack of internal layers;

selecting the closest available via pad in the virtual grid to each test point in a unit under test and assigning the selected via pad to the respective test point;

processing the first outer layer to provide a test pad aligned with each test point on the unit under test, a via pad for each test pad which is aligned with the assigned via pad in the virtual grid for the respective test point, and a connecting trace between each test pad and the associated via pad;

drilling a plated through hole through the board at each outer layer contact pad to connect the outer layer via pad with the aligned virtual grid via, whereby at least a plurality of test pads is connected to predetermined virtual grid vias; and

processing the second outer layer to provide a via pad aligned with each second via pad at the opposite end of each conductive trace connected to an assigned virtual grid via, drilling a plated through hole through each outer layer via pad to connect the second outer layer via pads with respective second via pads, providing a series of interface contact pads on the outer layer for connection to respective automated test equipment terminals, and connecting each interface contact pad with a respective second outer layer via pad with a conductive trace.

2. The method as claimed in claim 1, wherein the step of assigning each test point to the closest available virtual grid via includes determining whether any test points are unassignable to a virtual grid via, placing free via pads on the first outer layer in alignment with gaps between the circuits in the signal layers, connecting each unassignable test pad to a selected free via pad, placing a free via pad on the second outer layer in alignment with each free via pad on the first outer layer, and connecting the aligned free via pads on the first and second outer layers together by through hole plating.

3. The method as claimed in claim 1, including the steps of stacking a plurality of power and ground layers with the signal layers, each power and ground layer having a plurality of spaced, parallel conductive busses aligned with the busses in the other layers and a plurality of power and ground vias connected to each buss, providing power terminals on the second outer layer for connection to power sources in automated test equipment, connecting each power terminal to at least one of the busses, placing power and ground via pads on the first outer layer for providing power and ground connection to the unit under test, and connecting the power and ground via pads to selected power and ground vias on the power and ground layers by through hole plating.

4. The method as claimed in claim 3, wherein each inner signal layer is pre-fabricated to provide at least one conductive band around at least part of the periphery of the inner signal layer, the conductive band extending over the ends of the busses in the power and ground layers, and the step of connecting each power terminal to one of the busses comprises connecting each buss to a respective band by through hole plating, and connecting the bands to respective terminals in the second outer layer.