Silicon-on-silicon hybrid wafer assembly

• US 6,048,411 A
• Filed: 02/19/1998
• Issued: 04/11/2000
• Est. Priority Date: 05/12/1997
• Status: Expired due to Term

• Current Assignee: Silicon Genesis
• Original Assignee: Silicon Genesis
• Inventors: Henley, Francois J., Cheung, Nathan W.
• Primary Examiner(s): Bowers, Charles
• Assistant Examiner(s): CHRISTIANSON, KEITH ALAN
• Application Number:
  US09/025,966
• Time in Patent Office: 782 Days
• Field of Search: 117/915, 148/33, 148/33.2, 148/33.4, 148/33.5, 438/455, 438/458, 438/459, 438/514, 438/515, 438/526, 438/530, 438/977
• US Class Current: 148/33.5
• CPC Class Codes: B81C 1/0038 Processes for creating layers of materials not provided for in groups B81C1/00357 - B81C1/00373
• CPC Class Codes: B81C 2201/0191 Transfer of a layer from a carrier wafer to a device wafer
• CPC Class Codes: B81C 2201/0192 by cleaving the carrier wafer
• CPC Class Codes: H01L 21/187 by direct bonding
• CPC Class Codes: H01L 21/2007 Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer H01L21/2011 takes precedence; bonding of semiconductor wafers to semiconductor wafers for junction formation H01L21/187
• CPC Class Codes: H01L 21/2236 from or into a plasma phase
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 21/2658 of a molecular ion, e.g. decaborane
• CPC Class Codes: H01L 21/304 Mechanical treatment, e.g. grinding, polishing, cutting H01L21/30625 takes precedence
• CPC Class Codes: H01L 21/7624 using semiconductor on insulator [SOI] technology H01L21/76297 takes precedence; manufacture of integrated circuits on insulating substrates H01L21/84; silicon on sapphire [SOS] technology H01L21/86
• CPC Class Codes: H01L 21/76254 with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• CPC Class Codes: H01L 21/7813 leaving a reusable substrate, e.g. epitaxial lift off
• CPC Class Codes: Y10S 117/915 Separating from substrate
• CPC Class Codes: Y10S 156/93 Semiconductive product delaminating, e.g. delaminating emiconductive wafer from underlayer
• CPC Class Codes: Y10S 438/974 Substrate surface preparation
• CPC Class Codes: Y10S 438/977 Thinning or removal of substrate
• CPC Class Codes: Y10T 156/11 Methods of delaminating, per se; i.e. , separating at bonding face
• CPC Class Codes: Y10T 156/1158 Electromagnetic radiation applied to work for delamination [e.g., microwave, uv, ir, etc.]
• CPC Class Codes: Y10T 156/19 Delaminating means
• CPC Class Codes: Y10T 428/21 Circular sheet or circular blank
• CPC Class Codes: Y10T 428/24893 : including particulate material
• CPC Class Codes: Y10T 428/249956 : Void-containing component is inorganic

Abstract

A hybrid silicon-on-silicon substrate. A thin film (2101) of single-crystal silicon is bonded to a target wafer (46). A high-quality bond is formed between the thin film and the target wafer during a high-temperature annealing process. It is believed that the high-temperature annealing process forms covalent bonds between the layers at the interface (2305). The resulting hybrid wafer is suitable for use in integrated circuit manufacturing processes, similar to wafers with an epitaxial layer.

Claims

1. A hybrid silicon wafer comprising:

a thin film of single-crystal silicon material bonded to and electrically coupled to a silicon target wafer;

the thin film having an exposed cleaved surface.

2. The hybrid silicon wafer of claim 1 wherein the silicon target wafer is a single-crystal silicon wafer.

3. The hybrid silicon wafer of claim 1 wherein the thin film is less than about 15 microns thick.

4. The hybrid silicon wafer of claim 3 wherein the thin film has been separated from a donor wafer.

5. The hybrid silicon wafer of claim 1 wherein the thin film is beta bonded to the target wafer.

6. The hybrid silicon wafer of claim 1 wherein the thin film is securely bonded to the target wafer.

7. The hybrid silicon wafer of claim 1 further comprising electronic circuit devices disposed at least partially within the thin film.

8. The hybrid silicon wafer of claim 3 wherein the bonding process bonds the target wafer to the donor wafer at a temperature less than about 400°

C.

9. A hybrid silicon wafer comprising:

a single-crystal silicon donor wafer with an implanted layer of particles at a selected depth from a substrate-to-substrate interface;

a silicon target wafer bonded to the donor wafer at the substrate-to-substrate interface by a bonding process, the donor wafer being in electrical contact with the target wafer;

the implanted layer being less than about 15 microns from the substrate-to-substrate interface.

10. The hybrid silicon wafer of claim 9 wherein the implanted layer of particles comprises hydrogen ions.

11. A hybrid silicon wafer comprising:

a single-crystal silicon donor wafer with a layer of microbubbles at a selected depth from a substrate-to-substrate interface;

a silicon target wafer bonded to the donor wafer at the substrate-to-substrate interface, the donor wafer being in electrical contact with the target wafer;

the layer of microbubbles being less than about 15 microns from the substrate-to-substrate interface.