CMOS integrated circuit having PMOS and NMOS devices with different gate dielectric layers

• US 6,048,769 A
• Filed: 03/30/1998
• Issued: 04/11/2000
• Est. Priority Date: 02/28/1997
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Chau, Robert S.
• Primary Examiner(s): Fahmy, Wael M.
• Assistant Examiner(s): Pham, Long
• Application Number:
  US09/052,492
• Time in Patent Office: 743 Days
• Field of Search: 438/199, 438/275, 438/770, 438/775, 438/FOR 187, 438/FOR 216, 438/FOR 217, 438/FOR 218
• US Class Current: 438/275
• CPC Class Codes: H01L 21/823857 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS

Abstract

A CMOS integrated circuit having a PMOS and NMOS device with different gate dielectric layers. According to the present invention, an NMOS transistor is formed on a p-type conductivity region of a semiconductor substrate. The NMOS transistor has first gate dielectric layer formed on the p-type conductivity region. A PMOS transistor is formed on a n-type conductivity region of the semiconductor substrate. The PMOS transistor has a second gate dielectric layer wherein the second gate dielectric layer has a different composition than the first gate dielectric layer.

Claims

1. A method of forming an integrated circuit on a semiconductor substrate comprising the steps of:

forming a first dielectric layer on a first portion of said substrate;

forming a second dielectric layer on a second portion of said substrate and on said first dielectric layer over said first portion of said substrate;

forming a third dielectric layer over said second dielectric layer over said second portion of said substrate;

forming a first gate electrode over said second dielectric layer over said first portion of said substrate; and

forming a second gate electrode over said third dielectric layer over said second portion of said semiconductor substrate.

2. The method of claim 1 wherein said first substrate portion is n type conductivity and said second substrate portion is p type conductivity.

3. The method of claim 1 wherein said first dielectric layer is made of the same material as said third dielectric layer.

4. The method of claim 3 wherein said third and first dielectric layers are silicon dioxide.

5. The method of claim 1 wherein said second dielectric layer is a high dielectric constant material.

6. The method of claim 5 wherein said high dielectric constant material is silicon nitride.

7. A method of forming a CMOS integrated circuit comprising the steps of:

nitriding a first portion of a semiconductor substrate;

growing an oxide layer over said nitrided first portion of said semiconductor substrate and over a second portion of said semiconductor substrate;

nitridating said grown oxide layer over said first and said second portions of said semiconductor substrate; and

forming a first gate electrode over said nitridated grown oxide layer over said first portion of said semiconductor substrate and a second gate electrode over said nitridated grown oxide layer over said second portion of said semiconductor substrate portion.

8. The method of claim 7 wherein the step of nitriding said first portion of said semiconductor substrate comprises the steps of:

forming a sacrificial oxide layer over said first portion of said semiconductor substrate;

implanting nitrogen atoms through said sacrificial oxide layer and into said first portion of said semiconductor substrate; and

removing said sacrificial oxide layer.

9. The method of claim 7 wherein said first portion of said semiconductor substrate is p type conductivity and wherein said second portion of said semiconductor substrate is n type conductivity.

10. The method of claim 7 wherein said step of nitridating said oxide layer comprises a plasma nitridation process.

11. The method of claim 7 wherein said step of nitridating said oxide layer comprises a rapid thermal anneal in an ammonia ambient.