Method for fabricating a lateral RF MOS device with an non-diffusion source-backside connection

• US 6,048,772 A
• Filed: 05/04/1998
• Issued: 04/11/2000
• Est. Priority Date: 05/04/1998
• Status: Expired due to Term

• Current Assignee: Qorvo US, Inc. (Qorvo, Inc.)
• Original Assignee: Xemod, Inc. (Qorvo, Inc.)
• Inventors: D'Anna, Pablo Eugenio
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): Hack, Jonathan
• Application Number:
  US09/072,393
• Time in Patent Office: 708 Days
• Field of Search: 438/301, 438/305, 438/306
• US Class Current: 438/301
• CPC Class Codes: H01L 21/28052 the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer formed by metal ion implantation H01L21/28044
• CPC Class Codes: H01L 21/743 Making of internal connections, substrate contacts
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/4175 for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/66674 DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region making lateral high-voltage MISFETs with channel well and drain offset region H01L29/66659
• CPC Class Codes: H01L 29/7834 with a non-planar structure, e.g. the gate or the source or the drain being non-planar
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Methods of fabrication of a lateral RF MOS device having a non-diffusion connection between source and substrate are disclosed. In one embodiment, the lateral RF MOS device has an interdigitated silicided gate structure. In another embodiment, the lateral RF MOS device has a quasi-mesh silicided gate structure.

Claims

1. A method of forming a lateral RF MOS device for wireless communications with a non-diffusion source-substrate connection, starting from a substrate, said method comprising the steps of:

providing a semiconductor substrate having a principal surface and being of a first conductivity type;

growing an epi silicon layer on a top surface of said substrate, said epi layer having a first conductivity type;

growing a field oxide layer on a top surface of said epi layer;

forming a polysilicon gate;

forming a plurality of gate channels;

forming a plurality of drain regions and a plurality of source regions;

forming a silicided layer on said polysilicon gate; and

forming a plurality of metal contacts for connecting said plurality of gate channels, said plurality of drain regions and said plurality of source regions with an outside circuitry;

wherein said formation of said silicided layer on said polysilicon gate results in said lateral RF MOS device being utilized for wireless communications.

4. The method of claim 1, wherein a step of forming one said gate channel further comprises the steps of:

making a third mask to prepare a third layer area of said epi layer for implanting P⁺ boron dopant;

implanting P⁺ boron dopant into said third layer area of said epi layer to form a body contact region;

making a fourth mask to prepare a fourth layer area of said epi layer for implanting P boron dopant;

implanting P boron dopant into said fourth layer area of said epi layer to form a body region; and

diffusing said body contact region and said body region to form a channel region under said gate.

5. The method of claim 1, wherein a step of forming one said drain region and one said source region further comprises the steps of:

making a fifth mask to prepare a fifth layer area of said epi layer for implanting N phosphorous dopant;

implanting N phosphorous dopant into said fifth layer area of said epi layer to form an enhanced drift region;

making a sixth mask to prepare a sixth layer area of said epi layer for implanting N⁺ arsenic dopant;

implanting N⁺ arsenic dopant into said sixth layer area of said epi layer to form one said drain region and one said source region; and

diffusing said enhanced drift region, said source region and said drain region.

2. A method of forming a lateral RF MOS device for wireless communications with a non-diffusion source-substrate connection, starting from a substrate, said method comprising the steps of:

providing a semiconductor substrate having a principal surface and being of a first conductivity type;

growing an epi silicon layer on a top surface of said substrate, said epi layer having a first conductivity type;

growing a first layer of silicon dioxide;

depositing a layer of silicon nitride;

using a first mask to remove a part of said silicon nitride layer, to remove a part of said silicon dioxide layer, to mask an active device area and to form a field area;

implanting boron P⁺ dopant in said open field area;

performing said field area oxidation;

forming a polysilicon gate;

forming a plurality of gate channels;

forming a plurality of drain regions and a plurality of source regions;

forming a silicided layer on said polysilicon gate; and

forming a plurality of metal contacts for connecting said plurality of gate channels, said plurality of drain regions and said plurality of source regions with an outside circuitry.

3. A method of forming a lateral RF MOS device with a non-diffusion source-substrate connection, starting from a substrate, said method comprising the steps of:

providing a semiconductor substrate having a principal surface and being of a first conductivity type;

growing an epi silicon layer on a top surface of said substrate, said epi layer having a first conductivity type;

growing a field oxide layer on a top surface of said epi layer;

removing a part of said silicon nitride layer and a part of said first oxide layer from said active area;

growing a gate oxide layer in said active device area;

making deposit of a polysilicon layer;

using a second mask on said polysilicon layer to make a pattern gate structure;

depositing a siliciding metal selected from the group consisting of platinum, cobalt, tungsten, and titanium;

heating to form the metal silicide layer;

removing the unsilicided metal;

forming a plurality of gate channels;

forming a plurality of drain regions and a plurality of source regions;

forming a silicided layer on said polysilicon gate; and

forming a plurality of metal contacts for connecting said plurality of gate channels, said plurality of drain regions and said plurality of source regions with an outside circuitry.

6. A method of forming a lateral RF MOS device with a non-diffusion source-substrate connection, starting from a substrate, said method comprising the steps of:

providing a semiconductor substrate having a principal surface and being of a first conductivity type;

growing an epi silicon layer on a top surface of said substrate, said epi layer having a first conductivity type;

growing a field oxide layer on a top surface of said epi layer;

forming a polysilicon gate;

forming a plurality of gate channels;

forming a plurality of drain regions and a plurality of source regions;

forming a silicided layer on said polysilicon gate;

depositing a first insulating layer to cover all said source regions, all said drain regions, and all said gate regions;

opening said first insulating layer in contact areas to each said drain region, to each said gate region, and to each said source region by making a contact mask;

using a trench mask to make a trench in said epi layer in order to connect each said source area to said substrate;

making a first metal deposit in said trench;

making a first metal mask to pattern a plug inside said trench and to form said plurality of metal contacts connected to each said drain and to each said gate;

depositing a second insulating layer; and

making a pad mask to open said second insulating layer to make connections between said plurality of metal contacts connected to each said drain and each said gate and said outside circuitry;

whereby said lateral RF MOS device having an interdigitated gate structure is fabricated.

7. A method of forming a lateral RF MOS device with a non-diffusion source-substrate connection, starting from a substrate, said method comprising the steps of:

providing a semiconductor substrate having a principal surface and being of a first conductivity type;

growing an epi silicon layer on a top surface of said substrate, said epi layer having a first conductivity type;

growing a field oxide layer on a top surface of said epi layer;

forming a polysilicon gate;

forming a plurality of gate channels;

forming a plurality of drain regions and a plurality of source regions;

forming a silicided layer on said polysilicon gate;

depositing a first insulating layer to cover all said source regions, all said drain regions, and all said gate regions;

opening said first insulating layer in contact areas to each said drain region, to each said gate region, and to each said source region by making a contact mask;

using a trench mask to make a trench in said epi layer in order to connect each said source area to said substrate;

making a first metal deposit;

making a first metal mask to pattern a plug inside said trench and to form said plurality of metal contacts connected to each said drain and to each said gate;

depositing a second insulating layer;

making a via mask to each said contact region in each said drain region and in each said gate region;

making a second metal deposit;

making a second metal mask to pattern said plurality of metal contacts connected to each said drain and to each said gate;

depositing a third insulating layer; and

making a pad mask to open said third insulating layer to make connections between said plurality of metal contacts connected to each said drain and each said gate and said outside circuitry;

whereby said lateral RF MOS device having a quasi-mesh structure is fabricated.