Transistor having an improved salicided gate and method of construction

• US 6,048,784 A
• Filed: 12/15/1998
• Issued: 04/11/2000
• Est. Priority Date: 12/17/1997
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Kittl, Jorge A., Hong, Qi-Zhong
• Primary Examiner(s): Thomas, Tom
• Assistant Examiner(s): SOUW, BERNARD E
• Application Number:
  US09/212,189
• Time in Patent Office: 483 Days
• Field of Search: 438/592, 438/302, 438/303, 438/308, 438/798, 438/800, 257/388, 257/309, 257/401, 257/617
• US Class Current: 438/592
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/28052 the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer formed by metal ion implantation H01L21/28044
• CPC Class Codes: H01L 29/4941 with a barrier layer between the silicon and the metal or metal silicide upper layer, e.g. Silicide/TiN/Polysilicon
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518

Abstract

A method of fabricating a transistor having an improved salicided gate is provided. The method may include forming a gate (14) that is separated from a substrate (12) by a gate insulator (16). A spacer (22) may be formed proximate the gate (14) such that the spacer (22) exposes a top region (28) and a side region (30) of the gate (14). The top region (28) and the side region (30) of the gate (14) may be irradiated at an angle (38) to form a post amorphous region (32) within the gate (14). A reactive layer (42) may be formed adjacent the post amorphous region (32). A salicidation region (44) may be then formed between the post amorphous region (32) and the reactive layer (42). The reactive layer (42) may be removed to expose the salicidation region (44).

Claims

1. A method of forming an amorphous region in a gate of a transistor, the method comprising:

forming the gate separated from a substrate by a gate insulator;

forming a spacer outwardly from the gate, the spacer exposing a top region and a side region of the gate; and

irradiating the top region and side region of the gate using an ion beam directed at the gate at an angle to form a post amorphous region, the angle formed between the ion beam and an axis normal to a surface of the substrate and in the range of 5°

to 80°

.

2. The method of claim 1, and further comprising the steps of:

forming a reactive layer adjacent the post amorphous region;

forming a salicidation region between the post amorphous region and the reactive layer; and

removing the unreacted portion of the reactive layer.

3. The method of claim 2, wherein the reactive layer comprises titanium.

4. The method of claim 1, and further comprising the step of forming a buffer layer covering the substrate and the gate prior to the step of forming a spacer.

5. The method of claim 4, wherein the buffer layer comprises silicon dioxide.

6. The method of claim 1, wherein the step of forming a spacer comprises the steps of:

forming a spacer layer outwardly from the substrate and the gate; and

anisotropically etching the spacer layer past the top region of the gate to form the side region.

7. The method of claim 1, wherein the angle between the ion beam and the axis is approximately 45°

.

8. The method of claim 1, wherein the step of irradiating the top region and side region of the gate comprises the step of irradiating the top region and side region of the gate with germanium ions using an ion beam is directed at the gate at an angle to form a post amorphous region, the angle formed between the ion beam and an axis normal to a surface of the substrate.

9. The method of claim 8, wherein the ion beam has a dose of approximately 2E14 germanium ions/cm² and an energy of approximately 40 KeV.

10. The method of claim 1, wherein the step of forming a spacer outwardly from the gate comprises the step of forming a spacer outwardly from the gate, the spacer exposing a top region and a side region of the gate, the side region approximately one-half of the width of the gate.

11. A method of forming a semiconductor component with a transistor having a salicided gate, the method of forming the salicided gate comprising the steps of:

forming a gate separated from a substrate by a gate insulator;

forming a buffer layer outwardly from the substrate and the gate;

forming a spacer layer outwardly from the buffer layer;

anisotropically etching the spacer layer to form a spacer, the spacer exposing a post region of the gate and a gap region of the substrate;

irradiating the post region and the gap region using an ion beam directed at the gate at an angle to form a post amorphous region and a gap amorphous region, respectively;

wherein the angle is formed between the ion beam and an axis normal to a surface of the substrate and operates to reduce ion implantation damage to the substrate, the angle in the range of 5°

to 80°

;

forming a reactive layer adjacent the post amorphous region and the gap amorphous region;

forming a salicidation region between the post amorphous region and the reactive layer by thermally treating the reactive layer, the salicidation region of the gate forming, at least in part, the salicided gate of the transistor; and

removing the unreacted portion of reactive layer.

12. The method of claim 11, wherein the angle between the ion beam and the axis is approximately 45°

.

13. The method of claim 11, wherein the step of irradiating the post region and the gap region comprises the step of irradiating the post region and gap region with germanium ions using an ion beam directed at the gate at an angle to form a post amorphous region and a gap amorphous region, respectively.

14. The method of claim 13, wherein the ion beam has a dose of approximately 2E14 germanium ions/cm² and an energy of approximately 40 KeV.

15. The method of claim 11, wherein the salicidation region comprises C54 titanium silicide.

16. A method of forming a salicidation region in a gate of a transistor, the method comprising:

forming the gate separated from a substrate by a gate insulator;

forming a buffer layer outwardly from the substrate and the gate;

forming a spacer layer outwardly from the buffer layer;

etching the spacer layer anisotropically to form a spacer, the spacer exposing a top region and a side region of the gate;

forming a post amorphous region in the gate by irradiating the top region and side region of the gate using an ion beam directed at the gate at an angle, the angle formed between the ion beam and an axis normal to a surface of the substrate, the angle in the range of 5°

to 80°

;

removing the exposed portions of the buffer layer;

forming a reactive layer adjacent the post amorphous region;

heating the reactive layer to form a salicidation region between the post amorphous region and the reactive layer; and

removing the unreacted portion of the reactive layer.

17. The method of claim 16, wherein the angle between the ion beam and the axis is approximately 45°

.

18. The method of claim 16, wherein the ion beam comprises a beam of germanium ions.

19. The method of claim 16, wherein the spacer comprises a silicon nitride material.

20. The method of claim 16, wherein the salicidation region comprises C54 titanium silicide.