MOSFET device to reduce gate-width without increasing JFET resistance

• US 6,049,104 A
• Filed: 11/28/1997
• Issued: 04/11/2000
• Est. Priority Date: 11/28/1997
• Status: Expired due to Term

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: MagePower Semiconductor Corporation
• Inventors: Ly, Chanh, Koh, David Haksung, Weng, Shang-Lin, Hshieh, Fwu-Iuan
• Primary Examiner(s): MINTEL, WILLIAM A
• Application Number:
  US08/980,460
• Time in Patent Office: 865 Days
• Field of Search: 257/341, 257/329, 257/328, 257/335, 257/339, 438/230, 438/231, 438/944, 438/948
• US Class Current: 257/328
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: Y10S 438/944 Shadow
• CPC Class Codes: Y10S 438/948 Radiation resist

Abstract

The present invention discloses a method for fabricating a MOSFET device supported on a substrate. The method includes the steps of (a) growing an oxide layer on the substrate followed by depositing a polysilicon layer and applying a gate mask for performing an undercutting dry etch for patterning a plurality of polysilicon gates with a gate width narrower than a width of the gate mask; (b) applying the gate mask as body implant blocking mask for implanting a body dopant followed by removing the gate mask and carrying out a body diffusion for forming body regions; (c) applying a source blocking mask for implanting a source dopant to form a plurality of source regions; (d) forming an overlying insulation layer covering the MOSFET device followed by applying a dry oxide etch with a contact mask as a second mask to open a plurality of contact openings there through then removing the contact mask; (e) performing a high temperature reflow process for the overlying insulation layer and for driving the source regions into designed junction depths; (f) depositing a metal layer followed by applying a metal mask for patterning the metal layer to define a plurality of metal segments.

Claims

1. A vertical MOSFET transistor cell supported on a substrate of a first conductivity type functioning as a drain, the transistor cell comprising:

a polysilicon gate disposed above said substrate substantially at a center potion of said transistor cell; and

a body-dopant implant blocking-mask covering said gate and extending a distance δ

over edges of said polysilicon gate thus defining a body-dopant implant window having a width equal to D-2δ

wherein D is a distance between a gate and a neighboring gate.

2. The vertical MOSFET transistor cell as recited in claim 1 wherein:

a body implant region of a second conductivity type opposite to said first conductivity type disposed in said substrate aligned with said body dopant implant window.

3. The vertical MOSFET transistor cell as recited in claim 1 further comprising:

a source-dopant implant-block comprising an oxide block on top of said substrate disposed in a mid portion between said gate and a neighboring gate wherein said oxide block has a width less than two times of a lateral diffusion length of a body dopant.

4. The vertical MOSFET transistor cell as recited in claim 3 further comprising:

a source implant region of said first conductivity type disposed in said substrate aligned with a source-dopant implant window defined by an area between edges of said gate and said source-dopant implant-block.

5. The vertical MOSFET transistor cell as recited in claim 2 further comprising:

a second body implant region of said second conductivity type disposed immediately next to and aligned with edges of said gate having a depth shallower than said body dopant implant region aligned with said body dopant implant window.

6. A vertical MOSFET transistor cell supported on a substrate of a first conductivity type functioning as a drain, the transistor cell comprising:

a polysilicon gate disposed above said substrate substantially at a center potion of said transistor cell;

a source-dopant implant-block comprising an oxide block on top of said substrate disposed in a mid portion between said gate and a neighboring gate wherein said oxide block having a width less than two times of a lateral diffusion length of a body dopant;

a body-dopant implant blocking-mask covering said gate and extending a distance δ

over edges of said polysilicon gate thus defining a body-dopant implant window between edges of said body-dopant implant blocking mask and edges of said source-dopant implant-block having a width equal to D'"'"'-δ

wherein D'"'"' is a distance between edges of said gate and edges of said source-dopant implant-block.

7. The vertical MOSFET transistor cell as recited in claim 6 further comprising:

a body implant region of a second conductivity type opposite to said first conductivity type disposed in said substrate aligned with said body dopant implant window,

said under-gate-potion of said body region further includes an edge shallow body region disposed at an edge of said body region extending toward a center portion under said gate having a shallower depth than said body region.

8. The vertical MOSFET transistor cell as recited in claim 7 further comprising:

a source implant region of said first conductivity type disposed in said substrate aligned with a source-dopant implant window defined by an area between edges of said gate and said source-dopant implant-block.

9. The vertical MOSFET transistor cell as recited in claim 6 wherein:

a second body implant region of said second conductivity type disposed immediately next to and aligned with edges of said gate has a depth shallower than said body dopant implant region aligned with said body dopant implant window.

10. The vertical MOSFET transistor cell as recited in claim 9 wherein:

said second body-dopant region and said source implant region having substantially a same depth in said substrate.

16. The vertical MOSFET transistor cell as recited in claim 6 further comprising:

a central body-dopant implant region disposed right under said source implant-block formed as an oxide block said central body-dopant implant region disposed next to said body-dopant implant region aligned with said body-dopant implant window.

11. A vertical power transistor cell supported on a substrate of a first conductivity type functioning as a drain, the transistor cell comprising:

a gate disposed above said substrate substantially at a center potion of said transistor cell;

a source-dopant implant-block comprising an oxide block on top of said substrate disposed in a mid portion between said gate and a neighboring gate wherein said oxide block has a width larger than two times of a lateral diffusion length of a body dopant; and

a body-dopant implant blocking-mask covering said gate and extending a distance δ

over edges of said polysilicon gate thus defining a body-dopant implant window between edges of said body-dopant implant blocking mask and edges of said source-dopant implant-block having a width equal to D'"'"'-δ

wherein D'"'"' is a distance between edges of said gate and edges of said source-dopant implant-block.

12. The vertical power transistor cell as recited in claim 11 further comprising:

a body implant region of a second conductivity type opposite to said first conductivity type disposed in said substrate aligned with said body dopant implant window.

13. The vertical power transistor cell as recited in claim 12 further comprising:

a source implant region of said first conductivity type disposed in said substrate aligned with a source-dopant implant window defined by an area between edges of said gate and said source-dopant implant-block.

14. The vertical MOSFET transistor cell as recited in claim 11 further comprising:

a second body implant region of said second conductivity type disposed immediately next to and aligned with edges of said gate having a depth shallower than said body dopant implant region aligned with said body dopant implant window.

15. The vertical MOSFET transistor cell as recited in claim 14 wherein:

said second body-dopant region and said source implant region having substantially a same depth in said substrate.