Body driven SOI-MOS field effect transistor
First Claim
1. A semiconductor device comprising:
- a bottom electrode region;
an insulation layer extending on at least a top surface of said bottom electrode region;
a first semiconductor region of a first conductivity type formed over a first area of said insulation layer, said first semiconductor region having a first impurity concentration;
a second semiconductor region formed over a second area of said insulation layer, one side of said second semiconductor region being in contact directly with said first semiconductor region, said second semiconductor region having a second impurity concentration which is lower than said first impurity concentration, said second semiconductor region being one of a first conductivity type extrinsic semiconductor, a second conductivity type extrinsic semiconductor and an intrinsic semiconductor;
a third semiconductor region of said first conductivity type formed over a third area of said insulation layer, said third semiconductor region being in contact directly with an opposite side of said second semiconductor region, said third semiconductor region having a third impurity concentration which is higher than said second impurity concentration; and
a top electrode region formed in contact directly with a top surface of said second semiconductor region, said top electrode region being applied with a voltage signal,wherein said bottom electrode region is applied with a bottom gate voltage of an opposite polarity to said first conductivity type, andwherein ε
1/d1>
ε
2/d2, where ε
1 is a first dielectric constant of said second semiconductor region, d1 is a distance between a top of a depletion layer located within said second semiconductor region and a highest carrier concentration portion of a channel layer extending upward from a bottom interface of said second semiconductor region, ε
2 is a second dielectric constant of said insulation layer, and d2 is a thickness of said insulation layer.
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Accused Products
Abstract
In a body driven SOIMOSFET, a semiconductor layer extends over the insulator and comprises a first conductivity type high impurity concentration diffusion layer, a low impurity concentration region and another first conductivity type high impurity concentration diffusion layer which are in this order connected with each other. A second conductivity type high impurity concentration semiconductor layer is formed in contact with a top of the low impurity concentration region. A bottom electrode is formed within the insulation layer so that the bottom electrode is surrounded by the insulation layer. The bottom electrode is positioned under the low impurity concentration region and being separated by the insulation layer from the low impurity concentration region. It is important that the bottom electrode does not extend under the first conductivity high impurity concentration regions.
104 Citations
149 Claims
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1. A semiconductor device comprising:
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a bottom electrode region; an insulation layer extending on at least a top surface of said bottom electrode region; a first semiconductor region of a first conductivity type formed over a first area of said insulation layer, said first semiconductor region having a first impurity concentration; a second semiconductor region formed over a second area of said insulation layer, one side of said second semiconductor region being in contact directly with said first semiconductor region, said second semiconductor region having a second impurity concentration which is lower than said first impurity concentration, said second semiconductor region being one of a first conductivity type extrinsic semiconductor, a second conductivity type extrinsic semiconductor and an intrinsic semiconductor; a third semiconductor region of said first conductivity type formed over a third area of said insulation layer, said third semiconductor region being in contact directly with an opposite side of said second semiconductor region, said third semiconductor region having a third impurity concentration which is higher than said second impurity concentration; and a top electrode region formed in contact directly with a top surface of said second semiconductor region, said top electrode region being applied with a voltage signal, wherein said bottom electrode region is applied with a bottom gate voltage of an opposite polarity to said first conductivity type, and wherein ε
1/d1>
ε
2/d2, where ε
1 is a first dielectric constant of said second semiconductor region, d1 is a distance between a top of a depletion layer located within said second semiconductor region and a highest carrier concentration portion of a channel layer extending upward from a bottom interface of said second semiconductor region, ε
2 is a second dielectric constant of said insulation layer, and d2 is a thickness of said insulation layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45)
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46. A semiconductor device comprising:
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an insulation layer; a first semiconductor region of a first conductivity type formed over a first area of said insulation layer, said first semiconductor region having a first impurity concentration; a second semiconductor region formed over a second area of said insulation layer, one side of said second semiconductor region being in contact directly with said first semiconductor region, said second semiconductor region having a second impurity concentration which is lower than said first impurity concentration, said second semiconductor region being one of a first conductivity type extrinsic semiconductor, a second conductivity type extrinsic semiconductor and an intrinsic semiconductor; a third semiconductor region of said first conductivity type formed over a third area of said insulation layer, said third semiconductor region being in contact directly with an opposite side of said second semiconductor region, said third semiconductor region having a third impurity concentration which is higher than said second impurity concentration; and a top electrode region formed in contact directly with a top surface of said second semiconductor region, said top electrode region being applied with a voltage signal, wherein said insulation layer has a region having charges of an opposite polarity to said first conductivity type and extending at least under said second semiconductor region. - View Dependent Claims (47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68)
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69. A semiconductor device comprising:
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a bottom electrode region; an insulation layer extending on at least a top surface of said bottom electrode region; a first semiconductor region of a first conductivity type formed over a first area of said insulation layer, said first semiconductor region having a first impurity concentration; a second semiconductor region formed over a second area of said insulation layer, one side of said second semiconductor region being in contact directly with said first semiconductor region, said second semiconductor region having a second impurity concentration which is lower than said first impurity concentration, said second semiconductor region being one of a first conductivity type extrinsic semiconductor, a second conductivity type extrinsic semiconductor and an intrinsic semiconductor; a third semiconductor region of said first conductivity type formed over a third area of said insulation layer, said third semiconductor region being in contact directly with an opposite side of said second semiconductor region, said third semiconductor region having a third impurity concentration which is higher than said second impurity concentration; and a top electrode region formed in contact directly with a top surface of said second semiconductor region, said top electrode region being applied with a voltage signal, wherein said bottom electrode region is applied with a bottom gate voltage of an opposite polarity to said first conductivity type, and wherein Ccg>
Ccb, where Ccg is a first capacitance between said top electrode and a highest impurity concentration portion of an inversion region caused in said second semiconductor region, and Ccb is a first capacitance between said top electrode and said highest carrier concentration portion of said inversion region. - View Dependent Claims (70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113)
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114. A semiconductor device comprising:
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an insulation layer; a first semiconductor region of a first conductivity type formed over a first area of said insulation layer, said first semiconductor region having a first impurity concentration; a second semiconductor region formed over a second area of said insulation layer, one side of said second semiconductor region being in contact directly with said first semiconductor region, said second semiconductor region having a second impurity concentration which is lower than said first impurity concentration; a third semiconductor region of said first conductivity type formed over a third area of said insulation layer, said third semiconductor region being in contact directly with an opposite side of said second semiconductor region, said third semiconductor region having a third impurity concentration which is higher than said second impurity concentration; and a top electrode region formed in contact directly with a top surface of said second semiconductor region, said top electrode region being applied with a voltage signal, wherein said insulation layer has a region having charges of an opposite polarity to said first conductivity type and extending at least under said second semiconductor region, and wherein Ccg>
Ccb, where Ccg is a first capacitance between said top electrode and a highest impurity concentration portion of an inversion region caused in said second semiconductor region, and Ccb is a first capacitance as a coupling capacitance between (i) a channel extending upward from a bottom interface of said second semiconductor region and (ii) said first and third semiconductor regions through said insulation layer. - View Dependent Claims (115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 136)
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137. A semiconductor device comprising:
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an insulation layer; a semiconductor layer extending over said insulator and comprising a first conductivity type high impurity concentration diffusion layer, a low impurity concentration region and another first conductivity type high impurity concentration diffusion layer which are in this order connected with each other; a second conductivity type high impurity concentration semiconductor layer formed in contact with a top of said low impurity concentration region, said second semiconductor region being one of a first conductivity type extrinsic semiconductor, a second conductivity type extrinsic semiconductor and an intrinsic semiconductor; and a bottom electrode formed under said insulation layer. - View Dependent Claims (138, 139, 140, 141, 142, 143, 144, 145, 146, 147)
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148. A semiconductor device comprising:
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an insulation layer; a semiconductor layer extending over said insulator and comprising a first conductivity type high impurity concentration diffusion layer, a low impurity concentration region and another first conductivity type high impurity concentration diffusion layer which are in this order connected with each other; a second conductivity type high impurity concentration semiconductor layer formed in contact with a top of said low impurity concentration region, said second semiconductor region being one of a first conductivity type extrinsic semiconductor, a second conductivity type extrinsic semiconductor and an intrinsic semiconductor; and a bottom electrode formed within said insulation layer so that the bottom electrode is surrounded by said insulation layer, said bottom electrode being positioned under said low impurity concentration region and being separated by said insulation layer from said low impurity concentration region, wherein said bottom electrode has a width which is equal to or nearly equal to a width of said low impurity concentration region so that edges of said bottom electrode are positioned to just or almost correspond in plane view to edges of the low impurity concentration region.
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149. A semiconductor device comprising:
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an insulation layer; a semiconductor layer extending over said insulator and comprising a first conductivity type high impurity concentration diffusion layer, a low impurity concentration region and another first conductivity type high impurity concentration diffusion layer which are in this order connected with each other; a second conductivity type high impurity concentration semiconductor layer formed in contact with a top of said low impurity concentration region, said second semiconductor region being one of a first conductivity type extrinsic semiconductor, a second conductivity type extrinsic semiconductor and an intrinsic semiconductor; and a bottom electrode formed within said insulation layer so that the bottom electrode is surrounded by said insulation layer, said bottom electrode being positioned under said low impurity concentration region and being separated by said insulation layer from said low impurity concentration region, wherein said bottom electrode does not extend under said first conductivity high impurity concentration regions.
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Specification