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Semiconductor device including protective circuit with guard ring

  • US 6,049,111 A
  • Filed: 01/26/1998
  • Issued: 04/11/2000
  • Est. Priority Date: 06/30/1997
  • Status: Expired due to Fees
First Claim
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1. A semiconductor device comprising:

  • a semiconductor substrate of either an n-type or a p-type conductivity having formed therein an internal circuit which receives an input signal through an input pad, said internal circuit having a plurality of parasitic transistors which are connected to each other in parallel;

    a protection circuit including a MOS transistor having a source and a drain and formed in said semiconductor substrate to protect said internal circuit from a surge current applied to said input pad; and

    a guard ring, formed between said MOS transistor of said semiconductor substrate and said internal circuit, to cut off a leak current from said MOS transistor to said internal circuit, said guard ring including a well region having a conductivity type opposite to the conductivity type of said semiconductor substrate, and a pair of heavily doped impurity regions formed spaced apart from each other on the surface of said well region, having mutually different conductivity types, and having substantially equal voltages applied to have potentials with respect to the source of said MOS transistor,wherein there are formed a first parasitic transistor having a first region of said heavily doped impurity regions as the collector, said semiconductor substrate as the base, and the drain region of said MOS transistor as the emitter, said first region being identical in conductivity type with the well region and being located in said well region; and

    a second parasitic transistor having a second region of said heavily doped impurity regions in said well region as the emitter, the well region as the base, and said semiconductor substrate as the collector, said first parasitic transistor being connected in parallel to each of said parasitic transistors in said internal circuit and wherein the base and the collector of said first parasitic transistor are connected to the collector and the base of said second parasitic transistor respectively.

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