Semiconductor device including protective circuit with guard ring

• US 6,049,111 A
• Filed: 01/26/1998
• Issued: 04/11/2000
• Est. Priority Date: 06/30/1997
• Status: Expired due to Fees

• Current Assignee: OKI Electric Industry Company Limited
• Original Assignee: OKI Electric Industry Company Limited
• Inventors: Yamada, Hitoshi, Higuchi, Tsutomu
• Primary Examiner(s): Saadat, Mahshid
• Assistant Examiner(s): FENTY, JESSE A
• Application Number:
  US09/012,971
• Time in Patent Office: 806 Days
• Field of Search: 257/484, 257/355, 257/356, 257/358, 257/542, 257/173
• US Class Current: 257/355
• CPC Class Codes: H01L 21/765 by field effect H01L21/76264 takes precedence
• CPC Class Codes: H01L 27/0921 Means for preventing a bipolar, e.g. thyristor, action between the different transistor regions, e.g. Latchup prevention

Abstract

A semiconductor device includes a protection circuit and a guard ring. The guard ring is formed between a MOS transistor of a semiconductor substrate and internal circuits, to cut off a leak current from the MOS transistor to the internal circuits. The guard ring includes a well region and a pair of heavily doped impurity regions for med spaced apart from each other on the surface of the well region. The pair of doped regions have mutually different conductivity types and have substantially equal voltages applied to have potentials with respect to the source of the MOS transistor. There are formed a first parasitic transistor having one heavily doped impurity region as the collector, the semiconductor substrate as the base, and the drain of the MOS transistor as the emitter, the one heavily doped impurity region being identical in conductivity type with the well region; and a second parasitic transistor having the other heavily doped impurity region as the emitter, the well region as the base, and the semiconductor substrate as the collector. When the first parasitic transistor conducts, the second parasitic transistor conducts, which turns off the first parasitic transistor. Thus, the leak current is prevented from flowing from the MOS transistor through the first parasitic transistor to the internal circuits.

Claims

1. A semiconductor device comprising:

a semiconductor substrate of either an n-type or a p-type conductivity having formed therein an internal circuit which receives an input signal through an input pad, said internal circuit having a plurality of parasitic transistors which are connected to each other in parallel;

a protection circuit including a MOS transistor having a source and a drain and formed in said semiconductor substrate to protect said internal circuit from a surge current applied to said input pad; and

a guard ring, formed between said MOS transistor of said semiconductor substrate and said internal circuit, to cut off a leak current from said MOS transistor to said internal circuit, said guard ring including a well region having a conductivity type opposite to the conductivity type of said semiconductor substrate, and a pair of heavily doped impurity regions formed spaced apart from each other on the surface of said well region, having mutually different conductivity types, and having substantially equal voltages applied to have potentials with respect to the source of said MOS transistor,

wherein there are formed a first parasitic transistor having a first region of said heavily doped impurity regions as the collector, said semiconductor substrate as the base, and the drain region of said MOS transistor as the emitter, said first region being identical in conductivity type with the well region and being located in said well region; and

a second parasitic transistor having a second region of said heavily doped impurity regions in said well region as the emitter, the well region as the base, and said semiconductor substrate as the collector, said first parasitic transistor being connected in parallel to each of said parasitic transistors in said internal circuit and wherein the base and the collector of said first parasitic transistor are connected to the collector and the base of said second parasitic transistor respectively.

2. A semiconductor device according to claim 1, wherein of said pair of heavily doped impurity regions of said guard ring, the heavily doped impurity region opposite in conductivity type to said drain of said MOS transistor is arranged closer to said drain than the heavily doped impurity region of the other conductivity type.

3. A semiconductor device according to claim 1, wherein said pair of heavily doped impurity regions of said guard ring are connected to a power supply line and the first region identical in conductivity type with said well region is connected to said power supply line through the intermediary of a resistance.

4. A semiconductor device comprising:

a semiconductor substrate of either an n-type or a p-type conductivity having formed therein an internal circuit which receives an input signal through an input pad, said internal circuit having a plurality of parasitic transistors which are connected to each other in parallel;

a protection circuit including a MOS transistor having a source and a drain and formed in said semiconductor substrate to protect said internal circuit from a surge current applied to said input pad; and

a guard ring mechanism, formed between said MOS transistor of said semiconductor substrate and said internal circuit, to cut off a leak current from said MOS transistor to said internal circuit, said guard ring mechanism including a well region having a conductivity type opposite to the conductivity type of said semiconductor substrate, and a pair of heavily doped impurity regions formed spaced apart from each other on the surface of said well region, having mutually different conductivity types, and having substantially equal voltages applied to have potentials with respect to the source of said MOS transistor,

wherein there are formed a first parasitic transistor having a first region of said heavily doped impurity regions as the collector, said semiconductor substrate as the base, and the drain region of said MOS transistor as the emitter, said first region being identical in conductivity type with the well region and being located in said well region; and

a second parasitic transistor having a second region of said heavily doped impurity regions in said well region as the emitter, the well region as the base, and said semiconductor substrate as the collector, said first parasitic transistor being connected in parallel to each of said parasitic transistors in said internal circuit, and wherein the base and the collector of said first parasitic transistor are connected to the collector and the base of said second parasitic transistor respectively, and wherein conduction of said first parasitic transistor and said parasitic transistors in said internal circuit turns on said second parasitic transistor and then conduction of said second parasitic transistor turns off said first parasitic transistor and said parasitic transistors in said internal circuit.

5. A semiconductor device according to claim 4, wherein, of said pair of heavily doped impurity regions of said guard ring mechanism, the heavily doped impurity region opposite in conductivity type to said drain of said MOS transistor is arranged closer to said drain than the heavily doped impurity region of the other conductivity type.

6. A semiconductor device according to claim 4, wherein said pair of heavily doped impurity regions of said guard ring mechanism are connected to a power supply line and the first region identical in conductivity type with said well region is connected to said power supply line through the intermediary of a resistance.