Programmable logic array integrated circuit with general-purpose memory configurable as a random access or FIFO memory

• US 6,049,223 A
• Filed: 07/24/1996
• Issued: 04/11/2000
• Est. Priority Date: 03/22/1995
• Status: Expired due to Term

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Faria, Donald F., Lytle, Craig S.
• Primary Examiner(s): SANTAMAURO, JON P
• Application Number:
  US08/707,705
• Time in Patent Office: 1,357 Days
• Field of Search: 326/38-41, 365/221
• US Class Current: 326/40
• CPC Class Codes: H03K 19/17 using twistors
• CPC Class Codes: H03K 19/177 arranged in matrix form
• CPC Class Codes: H03K 19/17704 the logic functions being realised by the interconnection of rows and columns
• CPC Class Codes: H03K 19/17736 Structural details of routing resources

Abstract

A programmable logic device integrated circuit incorporating a memory block. The memory block (250) is a general-purpose memory configurable as a random access memory (RAM) or a first-in first-out (FIFO) memory. In one embodiment, the organization of memory block (250) may have variable word size and depth size. Memory block (250) is coupled to a programmable interconnect array (213). Signals from the programmable interconnect array (213) may be programmably coupled to the data, address, and control inputs of the memory block. Data output and status flag signals from the memory block are programmably coupled to the programmable interconnect array (213).

Claims

1. A programmable logic device integrated circuit comprising:

a first plurality of conductors, extending along a first dimension of a two-dimensional array;

a second plurality of conductors, extending along a second dimension of said two-dimensional array, wherein said second plurality of conductors is programmably coupled to said first plurality of conductors;

a plurality of logic array blocks, programmably coupled to said first plurality of conductors and second plurality of conductors;

a memory block, programmably coupled to said first plurality of conductors, wherein said memory block is programmably configurable as a random access memory in a first mode and a first-in, first-out memory in a second mode, and a memory organization of said memory block is programmably selectable by using a user-programmable memory bit; and

a pad coupled to provide addresses to an address bus of said memory block from an external source to said programmable logic device integrated circuit.

2. The programmable logic device integrated circuit of claim 1 wherein a word size and a depth size for said memory block are programmably selectable.

3. The programmable logic device integrated circuit of claim 1 wherein said memory organization of said memory block is configurable in a third mode, wherein said memory block has a first number of bits width and a second number of bits depth, and said memory block is configurable in a fourth mode, wherein said memory block has a third number of bits width, half said first number of bits width, and a fourth number of bits depth, twice said second number of bits depth.

4. The programmable logic device integrated circuit of claim 1 wherein said memory block is a dual-port memory.

5. The programmable logic device integrated circuit of claim 1 wherein said memory block is a single-port memory.

6. The programmable logic device integrated circuit of claim 1 wherein said first plurality of conductors is coupled to an address bus of said memory block.

7. The programmable logic device integrated circuit of claim 1 wherein said first plurality of conductors is coupled to a data bus of said memory block.

8. The programmable logic device integrated circuit of claim 1 wherein an output bus of said memory block is coupled to said first plurality of conductors.

9. The programmable logic device integrated circuit of claim 1 wherein said user-programmable memory bit is a floating gate device.

10. The programmable logic device integrated circuit of claim 1 wherein said user-programmable memory bit is an antifuse element.

11. The programmable logic device integrated circuit of claim 1 wherein said user-programmable memory bit is an SRAM cell.

12. The programmable logic device integrated circuit of claim 1 further comprising:

a global clock signal, coupled to at least one of said plurality of logic array blocks and said memory block.

13. The programmable logic device integrated circuit of claim 1 wherein said programmable logic device is configurable by in-system programming.

14. The programmable logic device integrated circuit of claim 1 wherein said memory block further comprises a plurality of control inputs, programmably coupled to said first plurality of conductors, wherein said plurality of control inputs controls operations of said memory block.

15. The programmable logic device integrated circuit of claim 1 wherein at least one logic array block of said plurality of logic array blocks is coupled directly to, without passing through said second plurality of conductors, a plurality of control inputs for said memory block.

16. The programmable logic device integrated circuit of claim 1 wherein said memory block generates a plurality of flag outputs, programmably coupled to said first plurality of conductors, wherein said plurality of flag outputs indicates a status of said memory block.

17. The programmable logic device integrated circuit of claim 1 wherein at least one logic element is coupled directly to said memory block without passing through said second plurality of conductors.

18. The programmable logic device integrated circuit of claim 1 wherein said second plurality of conductors is programmably coupled to said memory block using fully populated multiplexing.

19. The programmable logic device integrated circuit of claim 1 wherein said second plurality of conductors is programmably coupled to said memory block using partially populated multiplexing.

20. The programmable logic device integrated circuit of claim 1 further comprising:

a crossbar switch, coupled between said memory block and said second plurality of conductors, wherein said second plurality of conductors is programmably coupled to said crossbar switch using partially populated multiplexing.

21. The programmable logic device integrated circuit of claim 1 further comprising:

a plurality of input-output blocks, coupled to said plurality of logic array blocks; and

an output enable signal, programmably coupled to at least one of said plurality of input-output blocks and said memory block.

22. A digital processing system comprising:

a processing unit;

a memory, coupled to said processing unit; and

a programmable logic device integrated circuit as recited in claim 1, coupled to said processing unit and said memory.

133. The programmable logic device integrated circuit of claim 1 wherein said pad is directly coupled to said address bus of said memory block, without passing through said first plurality of conductors and said second plurality of conductors.

134. The programmable logic device integrated circuit of claim 1 wherein said memory block is operable in a first operation mode which is asynchronous and in a second operation mode which is synchronous, said operation modes being user selectable.

135. The programmable logic device integrated circuit of claim 16 wherein the plurality of flag outputs includes an ALMOST FULL flag output indicating that said memory block has a specified number of unoccupied memory locations, the specified number being user programmable.

136. The programmable logic device integrated circuit of claim 16 wherein the plurality of flag outputs includes an ALMOST EMPTY flag output indicating that said memory block has a specified number of occupied memory locations, the specified number being user programmable.

23. A programmable logic integrated circuit comprising:

a plurality of logic elements configurable to perform logical functions;

a programmable interconnect array configurable to interconnect signals between said logic elements; and

a first-in, first-out memory block, programmably coupled to said programmable interconnect array, wherein a memory organization of said first-in, first-out memory block is programmably configurable via a user-programmable memory bit.

24. The programmable logic device integrated circuit of claim 23 wherein a width of said first-in, first-out memory block is variable by configuring said user-programmable memory bit.

25. The programmable logic integrated circuit of claim 23 wherein a word size and a depth size for said first-in, first-out memory block are programmably selectable.

26. The programmable logic integrated circuit of claim 23 wherein said memory organization of said first-in, first-out memory block is configurable in a first mode to have a first number of bits width and a second number of bits depth, and configurable in a second mode to have a third number of bits width, half said first number of bits width, and a fourth number of bits depth, twice said second number of bits depth.

27. The programmable logic integrated circuit of claim 23 wherein said first-in, first-out memory block comprises a plurality of flags indicating status information of said first-in, first-out memory block, wherein said plurality of flags may be programmably coupled through said programmable interconnect array to drive logic of said programmable logic device.

28. The programmable logic integrated circuit of claim 23 wherein said first-in, first-out memory block comprises an ENABLE WRITE control input, coupled from said logic elements, to control writing of data into said first-in, first-out memory module.

29. The programmable logic integrated circuit of claim 23 wherein said first-in, first-out memory block comprises an ENABLE READ control input, coupled from said logic elements, to control reading of data from said first-in, first-out memory module.

30. The programmable logic integrated circuit of claim 23 wherein said first-in, first-out memory block comprises a CLEAR control input, coupled from said logic elements, to control resetting control logic within said first-in, first-out memory module.

31. The programmable logic integrated circuit of claim 23 wherein said first-in, first-out memory block generates an ALMOST FULL flag, user-programmable to indicate a number of unoccupied memory locations in said first-in, first-out memory, wherein said ALMOST FULL flag may be programmably coupled to said programmable interconnect array.

32. The programmable logic integrated circuit of claim 31 wherein said ALMOST FULL flag is FALSE when said number of unoccupied memory locations exceeds a user-selected value.

33. The programmable logic integrated circuit of claim 23 wherein said first-in, first-out memory block generates an ALMOST EMPTY flag, user-programmable to indicate a number of occupied memory locations in said first-in, first-out memory, wherein said ALMOST EMPTY flag may be programmably coupled to said programmable interconnect array.

34. The programmable logic integrated circuit of claim 23 wherein said ALMOST EMPTY flag is FALSE when said number of occupied memory locations exceeds a user-selected value.

35. The programmable logic integrated circuit of claims 32 or 34 wherein said user-selected value is stored in said programmable logic device using electrically erasable programmable read only memory cells.

137. The programmable logic integrated circuit of claim 23 wherein said first-in, first-out memory block is operable in a first operation mode which is asynchronous and in a second operation mode which is synchronous, said operation modes being user selectable.

138. The programmable logic integrated circuit of claim 23 further comprising a pad coupled to an address bus of said first-in, first-out memory block for providing addresses to said programmable logic integrated circuit from an external source without passing through said programmable interconnect array.

139. The programmable logic integrated circuit of claim 23 wherein said user-programmable memory bit is a floating point gate device.

140. The programmable logic integrated circuit of claim 23 wherein said user-programmable memory bit is an antifuse element.

141. The programmable logic integrated circuit of claim 23 wherein said user-programmable memory bit is a SRAM cell.

36. A programmable logic integrated circuit comprising:

a plurality of logic elements configurable to perform logical functions;

a programmable interconnect array configurable to interconnect signals between said plurality of logic elements; and

a memory block programmably coupled to said programmable interconnect array, said memory block programmably configurable as a random access memory in a first mode and a first-in, first-out memory in a second mode, said memory block comprising;

a data bus selectably accessible from said programmable interconnect array or a first pad, said first pad for coupling to components external to said programmable logic integrated circuit; and

an address bus accessible from a second pad.

37. The programmable logic integrated circuit of claim 36 wherein accessibility to said data bus from said programmable interconnect array or said first pad is programmably configurable.

38. The programmable logic integrated circuit of claim 36 wherein concurrent access to said memory block from said programmable interconnect array and said first pad is permitted.

39. The programmable logic integrated circuit of claim 36 wherein said address bus is accessible from said programmable interconnect array.

40. The programmable logic integrated circuit of claim 36 wherein said memory block further comprises:

an output bus, programmably configurable to provide data output to said programmable interconnect array or a third pad.

41. The programmable logic integrated circuit of claim 40 wherein said output bus is programmably coupled to provide data output to said data bus.

42. The programmable logic integrated circuit of claim 36 wherein said memory block is dual-ported.

43. The programmable logic integrated circuit of claim 36 wherein said memory block is single-ported.

44. The programmable logic integrated circuit of claim 36 wherein said memory block further comprises:

a plurality of control inputs to control operation of said memory block, wherein said plurality of control inputs is programmably coupled to the programmable interconnect array.

45. The programmable logic integrated circuit of claim 36 wherein said memory block further comprises:

a busy flag signal to indicate whether a read port and a write port are addressing a similar memory location.

46. The programmable logic integrated circuit of claim 36 wherein said memory block further comprises:

a first portion of memory cells; and

a second portion of memory cells, wherein said first and second portions are coupled in parallel.

47. The programmable logic integrated circuit of claim 36 wherein a memory organization of said memory block is programmably configurable via at least one user-programmable memory cell.

48. The programmable logic device integrated circuit of claim 47 wherein said memory organization of said memory block is configurable in a third mode to have a first number of bits width and a second number of bits depth, and configurable in a fourth mode to have a third number of bits width, half said first number of bits width, and a fourth number of bits depth, twice said second number of bits depth.

142. The programmable logic integrated circuit of claim 36 wherein said second pad is directly coupled to said address bus, without passing through said programmable interconnect array.

143. The programmable logic integrated circuit of claim 36 wherein said memory block is operable in a first operation mode which is asynchronous and in a second operation mode which is synchronous, said operation modes being user selectable.

49. A programmable logic integrated circuit comprising:

a plurality of logic elements configurable to perform logical functions;

a programmable interconnect array configurable to interconnect signals between said plurality of logic elements; and

a memory module, programmably coupled to said programmable interconnect array, wherein said memory module programmably is configurable as a random access memory in a first mode and a first-in, first-out memory in a second mode, and said memory module comprises;

a read address bus accessible from said programmable interconnect array or a first pad, said first pad coupled to provide data external to said programmable logic integrated circuit, whereby said read address bus provides memory addresses for reading data from said memory module.

50. The programmable logic integrated circuit of claim 49 wherein said memory module further comprises:

a write address bus accessible from said programmable interconnect array or said first pad, whereby said write address bus provides memory addresses for writing data to said memory block.

51. The programmable logic integrated circuit of claim 49 wherein said memory module further comprises:

a data bus accessible from said programmable interconnect array or said first pad.

144. The programmable logic integrated circuit of claim 49 wherein said first pad is directly coupled to said address bus without passing through said programmable interconnect array.

145. The programmable logic integrated circuit of claim 49 wherein said memory module is operable in a first operation mode which is asynchronous and in a second operation mode which is synchronous, said operation mode being user selectable.

52. A programmable logic integrated circuit comprising:

a first plurality of conductors, extending along a first dimension of a two-dimensional array;

a second plurality of conductors, extending along a second dimension of said two-dimensional array, wherein said second plurality of conductors is programmably coupled to said first plurality of conductors;

a plurality of logic array blocks, programmably coupled to said first plurality of conductors and second plurality of conductors;

a memory block, programmably coupled to said first plurality of conductors, wherein said memory block is a dual-port memory, and a memory organization of said memory block is programmably selectable a user-programmable memory bit; and

a pad coupled to provide addresses to an address bus of said memory block from an external source to said programmable logic device integrated circuit.

53. The programmable logic device integrated circuit of claim 52 wherein a word size and a depth size for said memory block are programmably selectable.

54. The programmable logic device integrated circuit of claim 52 wherein said memory organization of said memory block is configurable in a first mode to have a first number of bits width and a second number of bits depth, and in a second mode to have a third number of bits width, half said first number of bits width, and a fourth number of bits depth, twice said second number of bits depth.

55. The programmable logic device integrated circuit of claim 52 wherein said first plurality of conductors is coupled to an address bus of said memory block.

56. The programmable logic device integrated circuit of claim 52 wherein said first plurality of conductors is coupled to a data bus of said memory block.

57. The programmable logic device integrated circuit of claim 52 wherein an output bus of said memory block is coupled to said first plurality of conductors.

58. The programmable logic device integrated circuit of claim 52 wherein said user-programmable memory bit is a floating gate device.

59. The programmable logic device integrated circuit of claim 52 wherein said user-programmable memory bit is an antifuse element.

60. The programmable logic device integrated circuit of claim 52 wherein said user-programmable memory bit is an SRAM cell.

61. The programmable logic device integrated circuit of claim 52 further comprising:

a global clock signal, coupled to at least one of said plurality of logic array blocks and said memory block.

62. The programmable logic device integrated circuit of claim 52 wherein said programmable logic device is configurable by in-system programming.

63. The programmable logic device integrated circuit of claim 52 wherein said memory block further comprises a plurality of control inputs, programmably coupled to said first plurality of conductors, wherein said plurality of control inputs controls operations of said memory block.

64. The programmable logic device integrated circuit of claim 52 wherein at least one logic array block of said plurality of logic array blocks is coupled directly to, without passing through said second plurality of conductors, a plurality of control inputs for said memory block.

65. The programmable logic device integrated circuit of claim 52 wherein said memory block generates a plurality of flag outputs, programmably coupled to said first plurality of conductors, wherein said plurality of flag outputs indicates a status of said memory block.

66. The programmable logic device integrated circuit of claim 52 wherein at least one logic element is coupled directly to said memory block without passing through said second plurality of conductors.

67. The programmable logic device integrated circuit of claim 52 wherein said second plurality of conductors is programmably coupled to said memory block using fully populated multiplexing.

68. The programmable logic device integrated circuit of claim 52 wherein said second plurality of conductors is programmably coupled to said memory block using partially populated multiplexing.

69. The programmable logic device integrated circuit of claim 52 further comprising:

a crossbar switch, coupled between said memory block and said second plurality of conductors, wherein said second plurality of conductors is programmably coupled to said crossbar switch using partially populated multiplexing.

70. The programmable logic device integrated circuit of claim 52 further comprising:

a plurality of input-output blocks, coupled to said plurality of logic array blocks; and

an output enable signal, programmably coupled to at least one of said plurality of input-output blocks and said memory block.

71. A digital processing system comprising:

a processing unit;

a memory, coupled to said processing unit; and

a programmable logic device integrated circuit as recited in claim 52, coupled to said processing unit and said memory.

146. The programmable logic device integrated circuit of claim 52 wherein said pad is directly coupled to said address bus of said memory block, without passing through said first plurality of conductors and said second plurality of conductors.

147. The programmable logic device integrated circuit of claim 52 wherein said memory block is operable in a first operation mode which is asynchronous and in a second operation mode which is synchronous, said operation modes being user selectable.

148. The programmable logic device integrated circuit of claim 65 wherein plurality of flag outputs includes an ALMOST FULL flag output indicating that said memory block has a specified number of unoccupied memory locations, the specified number being user programmable.

149. The programmable logic device integrated circuit of claim 65 wherein plurality of flag outputs includes an ALMOST EMPTY flag output indicating that said memory block has a specified number of occupied memory locations, the specified number being user programmable.

72. A programmable logic device integrated circuit comprising:

a first plurality of conductors, extending along a first dimension of a two-dimensional array;

a memory block, programmably coupled to said first plurality of conductors, and wherein a memory organization of said memory block is programmably selectable by using a user-programmable memory bit;

a second plurality of conductors, extending along a second dimension of said two-dimensional array, wherein said second plurality of conductors is programmably coupled to said first plurality of conductors;

a plurality of logic array blocks, programmably coupled to said first plurality of conductors and second plurality of conductors, wherein at least one logic array block of said plurality of logic array blocks is coupled directly to, without passing through said second plurality of conductors, a plurality of control inputs for said memory block; and

a pad coupled to provide addresses to an address bus of said memory block from a source external to said programmable logic device integrated circuit.

73. The programmable logic device integrated circuit of claim 72 wherein a word size and a depth size for said memory block are programmably selectable.

74. The programmable logic device integrated circuit of claim 72 wherein said memory organization of said memory block is configurable in a first mode to have a first number of bits width and a second number of bits depth, and in a second mode to have a third number of bits width, half said first number of bits width, and a fourth number of bits depth, twice said second number of bits depth.

75. The programmable logic device integrated circuit of claim 72 wherein said memory block is a single-port memory.

76. The programmable logic device integrated circuit of claim 72 wherein said first plurality of conductors is coupled to an address bus of said memory block.

77. The programmable logic device integrated circuit of claim 72 wherein said first plurality of conductors is coupled to a data bus of said memory block.

78. The programmable logic device integrated circuit of claim 72 wherein an output bus of said memory block is coupled to said first plurality of conductors.

79. The programmable logic device integrated circuit of claim 72 wherein said user-programmable memory bit is a floating gate device.

80. The programmable logic device integrated circuit of claim 72 wherein said user-programmable memory bit is an antifuse element.

81. The programmable logic device integrated circuit of claim 72 wherein said user-programmable memory bit is an SRAM cell.

82. The programmable logic device integrated circuit of claim 72 further comprising:

a global clock signal, coupled to at least one of said plurality of logic array blocks and said memory block.

83. The programmable logic device integrated circuit of claim 72 wherein said programmable logic device integrated circuit is configurable by in-system programming.

84. The programmable logic device integrated circuit of claim 72 wherein said memory block further comprises a plurality of control inputs, programmably coupled to said first plurality of conductors, wherein said plurality of control inputs controls operations of said memory block.

85. The programmable logic device integrated circuit of claim 72 wherein said memory block generates a plurality of flag outputs, programmably coupled to said first plurality of conductors, wherein said plurality of flag outputs indicates a status of said memory block.

86. The programmable logic device integrated circuit of claim 72 wherein at least one logic element is coupled directly to said memory block without passing through said second plurality of conductors.

87. The programmable logic device integrated circuit of claim 72 wherein said second plurality of conductors is programmably coupled to said memory block using fully populated multiplexing.

88. The programmable logic device integrated circuit of claim 72 wherein said second plurality of conductors is programmably coupled to said memory block using partially populated multiplexing.

89. The programmable logic device integrated circuit of claim 72 further comprising:

a crossbar switch, coupled between said memory block and said second plurality of conductors, wherein said second plurality of conductors is programmably coupled to said crossbar switch using partially populated multiplexing.

90. The programmable logic device integrated circuit of claim 72 further comprising:

a plurality of input-output blocks, coupled to said plurality of logic array blocks; and

an output enable signal, programmably coupled to at least one of said plurality of input-output blocks and said memory block.

91. A digital processing system comprising:

a processing unit;

a memory, coupled to said processing unit; and

a programmable logic device integrated circuit as recited in claim 72, coupled to said processing unit and said memory.

150. The programmable logic device integrated circuit of claim 72 wherein said pad is directly coupled to said address bus of said memory block, without passing through said first plurality of conductors and said second plurality of conductors.

151. The programmable logic device integrated circuit of claim 72 wherein said memory block is operable in a first operation mode which is asynchronous and in a second operation mode which is synchronous, said operation modes being user selectable.

152. The programmable logic device integrated circuit of claim 85 wherein plurality of flag outputs includes an ALMOST FULL flag output indicating that said memory block has a specified number of unoccupied memory locations, the specified number being user programmable.

153. The programmable logic device integrated circuit of claim 85 wherein plurality of flag outputs includes an ALMOST EMPTY flag output indicating that said memory block has a specified number of occupied memory locations, the specified number being user programmable.

92. A programmable logic device integrated circuit comprising:

a first plurality of conductors, extending along a first dimension of a two-dimensional array;

a second plurality of conductors, extending along a second dimension of said two-dimensional array, wherein said second plurality of conductors is programmably coupled to said first plurality of conductors;

a plurality of logic array blocks, programmably coupled to said first plurality of conductors and second plurality of conductors;

a memory block, programmably coupled to said first plurality of conductors, wherein said memory block generates a plurality of flag outputs, programmably coupled to said first plurality of conductors, wherein said plurality of flag outputs indicates a status of said memory block and, wherein a memory organization of said memory block is programmably selectable by using a user-programmable memory bit; and

a pad coupled to provide addresses to an address bus of said memory block from a source external to said programmable logic device integrated circuit.

93. The programmable logic device integrated circuit of claim 92 wherein a word size and a depth size for said memory block are programmably selectable.

94. The programmable logic device integrated circuit of claim 92 wherein said memory organization of said memory block is configurable in a first mode to have a first number of bits width and a second number of bits depth, and in a second mode to have a third number of bits width, half said first number of bits width, and a fourth number of bits depth, twice said second number of bits depth.

95. The programmable logic device integrated circuit of claim 92 wherein said memory block is a single-port memory.

96. The programmable logic device integrated circuit of claim 92 wherein said first plurality of conductors is coupled to an address bus of said memory block.

97. The programmable logic device integrated circuit of claim 92 wherein said first plurality of conductors is coupled to a data bus of said memory block.

98. The programmable logic device integrated circuit of claim 92 wherein an output bus of said memory block is coupled to said first plurality of conductors.

99. The programmable logic device integrated circuit of claim 92 wherein said user-programmable memory bit is a floating gate device.

100. The programmable logic device integrated circuit of claim 92 wherein said user-programmable memory bit is an antifuse element.

101. The programmable logic device integrated circuit of claim 92 wherein said user-programmable memory bit is an SRAM cell.

102. The programmable logic device integrated circuit of claim 92 further comprising:

a global clock signal, coupled to at least one of said plurality of logic array blocks and said memory block.

103. The programmable logic device integrated circuit of claim 92 wherein said programmable logic device is configurable by in-system programming.

104. The programmable logic device integrated circuit of claim 92 wherein said memory block further comprises a plurality of control inputs, programmably coupled to said first plurality of conductors, wherein said plurality of control inputs controls operations of said memory block.

105. The programmable logic device integrated circuit of claim 92 wherein at least one logic element is coupled directly to said memory block without passing through said second plurality of conductors.

106. The programmable logic device integrated circuit of claim 92 wherein said second plurality of conductors is programmably coupled to said memory block using fully populated multiplexing.

107. The programmable logic device integrated circuit of claim 92 wherein said second plurality of conductors is programmably coupled to said memory block using partially populated multiplexing.

108. The programmable logic device integrated circuit of claim 92 further comprising:

a crossbar switch, coupled between said memory block and said second plurality of conductors, wherein said second plurality of conductors is programmably coupled to said crossbar switch using partially populated multiplexing.

109. The programmable logic device integrated circuit of claim 92 further comprising:

a plurality of input-output blocks, coupled to said plurality of logic array blocks; and

an output enable signal, programmably coupled to at least one of said plurality of input-output blocks and said memory block.

110. A digital processing system comprising:

a processing unit;

a memory, coupled to said processing unit; and

a programmable logic device integrated circuit as recited in claim 92, coupled to said processing unit and said memory.

154. The programmable logic device integrated circuit of claim 92 wherein said pad is directly coupled to said address bus of said memory block, without passing through said first plurality of conductors and said second plurality of conductors.

155. The programmable logic device integrated circuit of claim 92 wherein said memory block is operable in a first operation mode which is asynchronous and in a second operation mode which is synchronous, said operation modes being user selectable.

111. A programmable logic integrated circuit comprising:

a plurality of logic elements configurable to perform logical functions;

a programmable interconnect array configurable to interconnect signals between said plurality of logic elements; and

a memory block programmably coupled to said programmable interconnect array, wherein said memory block is dual-ported and comprises;

a data bus selectably accessible from said programmable interconnect array or a first pad, said first pad for coupling to components external to said programmable logic integrated circuit; and

an address bus accessible from a second pad.

112. The programmable logic integrated circuit of claim 111 wherein accessibility to said data bus from said programmable interconnect array or said first pad is programmably configurable.

113. The programmable logic integrated circuit of claim 114 wherein concurrent access to said memory block from said programmable interconnect array and said first pad is permitted.

114. The programmable logic integrated circuit of claim 111 wherein said address bus is accessible from said programmable interconnect array.

115. The programmable logic integrated circuit of claim 111 wherein said memory block further comprises:

an output bus, programmably configurable to provide data output to said programmable interconnect array or a third pad.

116. The programmable logic integrated circuit of claim 115 wherein said output bus is programmably coupled to provide data output to said data bus.

117. The programmable logic integrated circuit of claim 111 wherein said memory block further comprises:

a plurality of control inputs to control operation of said memory block, wherein said plurality of control inputs is programmably coupled to the programmable interconnect array.

118. The programmable logic integrated circuit of claim 111 wherein said memory block further comprises:

a busy flag signal to indicate whether a read port and a write port are addressing a similar memory location.

119. The programmable logic integrated circuit of claim 111 wherein said memory block further comprises:

a first portion of memory cells; and

a second portion of memory cells, wherein said first and second portions are coupled in parallel.

120. The programmable logic integrated circuit of claim 111 wherein a memory organization of said memory block is programmably configurable by using at least one user-programmable memory cell.

121. The programmable logic device integrated circuit of claim 120 wherein said memory organization of said memory block is configurable in a first mode to have a first number of bits width and a second number of bits depth, and in a second mode to have a third number of bits width, half said first number of bits width, and a fourth number of bits depth, twice said second number of bits depth.

156. The programmable logic integrated circuit of claim 111 wherein said second pad is directly coupled to said address bus, without passing through said programmable interconnect array.

157. The programmable logic integrated circuit of claim 111 wherein said memory block is operable in a first operation mode which is asynchronous and in a second operation mode which is synchronous, said operation modes being user selectable.

122. A programmable logic integrated circuit comprising:

a plurality of logic elements configurable to perform logical functions;

a programmable interconnect array configurable to interconnect signals between said plurality of logic elements; and

a memory block programmably coupled to said programmable interconnect array, said memory block comprising;

a busy flag signal to indicate whether a read port and a write port are addressing a similar memory location; and

a data bus selectably accessible from said programmable interconnect array or a first pad, said first pad for coupling to components external to said programmable logic integrated circuit; and

an address bus accessible from a second pad.

123. The programmable logic integrated circuit of claim 122 wherein accessibility to said data bus from said programmable interconnect array or said first pad is programmably configurable.

124. The programmable logic integrated circuit of claim 122 wherein concurrent access to said memory block from said programmable interconnect array and said first pad is permitted.

125. The programmable logic integrated circuit of claim 122 wherein said address bus is accessible from said programmable interconnect array.

126. The programmable logic integrated circuit of claim 122 wherein said memory block further comprises:

an output bus, programmably configurable to provide data output to said programmable interconnect array or a third pad.

127. The programmable logic integrated circuit of claim 126 wherein said output bus is programmably coupled to provide data output to said data bus.

128. The programmable logic integrated circuit of claim 122 wherein said memory block is single-ported.

129. The programmable logic integrated circuit of claim 122 wherein said memory block further comprises:

a plurality of control inputs to control operation of said memory block, wherein said plurality of control inputs is programmably coupled to the programmable interconnect array.

130. The programmable logic integrated circuit of claim 122 wherein said memory block further comprises:

a first portion of memory cells; and

a second portion of memory cells, wherein said first and second portions are coupled in parallel.

131. The programmable logic integrated circuit of claim 122 wherein a memory organization of said memory block is programmably configurable by using at least one user-programmable memory cell.

132. The programmable logic device integrated circuit of claim 131 wherein said memory organization of said memory block is configurable in a first mode to have a first number of bits width and a second number of bits depth, and in a second mode to have a third number of bits width, half said first number of bits width, and a fourth number of bits depth, twice said second number of bits depth.

158. The programmable logic integrated circuit of claim 122 wherein said second pad is directly coupled to said address bus, without passing through said programmable interconnect array.

159. The programmable logic integrated circuit of claim 122 wherein said memory block is operable in a first operation mode which is asynchronous and in a second operation mode which is synchronous, said operation modes being user selectable.

160. A programmable logic device integrated circuit comprising:

means for programmably conducting logic signals along a first dimension of a two-dimension array;

means for programmably conducting logic signal along a second dimension of said two-dimensional array, said means for programmably conducting said logic signals along said second dimension being programmably coupled to said means for programmably conducting said logic signals along said first dimension;

means for programmably implementing logical functions coupled to said means for programmably conducting said logic signals along said second dimension and said means for programmably conducting said logic signals along said first dimension;

means for storing data coupled to said means for programmably conducting said logic signals along said first dimension;

means for programmably configuring said means for storing data as a random access memory in a first mode and as a first-in, first-out memory in a second mode; and

means for providing addresses to an address bus of said means for storing data from a source external to said programmable logic device integrated circuit.

161. The programmable logic device integrated circuit of claim 160 wherein said means for providing said addresses is directly coupled to said address bus of said means for storing data, without passing through said means for programmably conducting said logic signals along said second dimension and said means for programmably said conducting logic signals along said first dimension.

162. The programmable logic device integrated circuit of claim 160 wherein said means for storing data is operable in a first operation mode which is asynchronous and in a second operation mode which is synchronous, said operation modes being user selectable.