Input/output interface circuitry for programmable logic array integrated circuit devices

• US 6,049,225 A
• Filed: 02/13/1998
• Issued: 04/11/2000
• Est. Priority Date: 08/24/1995
• Status: Expired due to Term

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Huang, Joseph, Cliff, Richard G., Reddy, Srinivas T.
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): Tan, Vibol
• Application Number:
  US09/023,369
• Time in Patent Office: 788 Days
• Field of Search: 326/39, 326/41, 326/101, 326/40
• US Class Current: 326/41
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/17744 for input/output signals

Abstract

In a programmable logic array integrated circuit device, various techniques are used to increase the flexibility with which the core logic of the device can be connected to the input and/or output pins of the device. While the techniques shown greatly increase circuit flexibility, they avoid the unnecessary overhead of interconnectivity which is completely general.

Claims

1. A programmable logic array device comprising:

a plurality of regions of programmable logic disposed on said device, each of said regions being programmable to produce an output signal which is any of a plurality of logic functions of a plurality of input signals applied to that region;

a plurality of conductors extending adjacent to said regions, each said conductor being selectively usable for conveying signals to, from, and between said regions;

a plurality of device output pins associated with said regions;

a multiplicity of first programmable logic connectors, each of which receives signals from a respective one of a multiplicity of subpluralities of said conductors, and each of which is programmable to produce a signal which is indicative of at least one of the signals it receives; and

a plurality of second programmable logic connectors, each of which receives signals produced by a plurality of said first programmable logic connectors, and each of which is programmable to produce a signal which is indicative of at least one of the signals it receives for application to a respective one of said device output pins;

wherein;

one of said first programmable logic connectors and a subplurality of said second programmable logic connectors are programmable to produce a signal which is indicative of a signal received by said one first programmable logic connector for application to any one of a subplurality of said device output pins.

2. The apparatus defined in claim 1 wherein said regions are disposed on said device in a linear array, wherein said linear array is one of a plurality of similar linear arrays disposed on said device, and wherein each of said second programmable logic connectors receives signals only from first programmable logic connectors which in turn only receive signals from conductors extending adjacent to regions in one of said linear arrays.

3. A programmable logic array device comprising:

a plurality of regions of programmable logic disposed on said device, each of said regions being programmable to produce an output signal which is any of a plurality of logic functions of a plurality of input signals applied to that region;

a plurality of conductors extending adjacent to said regions, each said conductor being selectively usable for conveying signals to, from, and between said regions;

a plurality of device output pins associated with said regions;

a multiplicity of first programmable logic connectors, each of which receives signals from a respective one of a multiplicity of subpluralities of said conductors, and each of which is programmable to produce a signal which is indicative of at least one of the signals it receives; and

a plurality of second programmable logic connectors, each of which receives signals produced by a plurality of said first programmable logic connectors, and each of which is programmable to produce a signal which is indicative of at least one of the signals it receives for application to a respective one of said device output pins;

wherein;

one of said first programmable logic connectors and a subplurality of said second programmable logic connectors are programmable to produce a signal which is indicative of a signal received by said one first programmable logic connector for application to a subplurality of said device output pins.