Level converter

• US 6,049,226 A
• Filed: 07/23/1998
• Issued: 04/11/2000
• Est. Priority Date: 07/23/1997
• Status: Expired due to Fees

• Current Assignee: Lantiq Beteiligungs-GmbH & Company KG (Intel Corporation)
• Original Assignee: Siemens AG
• Inventors: Latzel, Thomas, Sporrer, Christian
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): LE, THANH TAM T
• Application Number:
  US09/121,508
• Time in Patent Office: 628 Days
• Field of Search: 326/68, 326/73, 326/74, 326/80, 326/81, 326/83, 326/86, 326/121
• US Class Current: 326/68
• CPC Class Codes: H03K 3/356147 using pass gates

Abstract

A level converter for converting two input levels into two output levels includes two push-pull paths having inputs forming a level converter input and outputs coupled crosswise and forming two level converter outputs. The level converter can be produced by using integrated circuit technology. The circuit operates without current in a quiescent state and recharging currents flow only during switching processes.

Claims

1. A level converter, comprising:

a level converter input, a level converter output and an inverted level converter output;

a first push-pull input stage having first and second inputs and first and second outputs;

first and second transistors each having first and second outputs and a control input;

said first input of said first push-pull input stage connected to said level converter input, and said first output of said first push-pull input stage connected to the control input of said first transistor;

said second output of said first push-pull input stage connected to the first output of said first transistor, to the first output of said second transistor and to said level converter output;

an inverter;

a second push-pull input stage having first and second inputs and first and second outputs;

third and fourth transistors each having first and second outputs and a control input;

said first input of said second push-pull input stage connected through said inverter to said level converter input, and said first output of said second push-pull input stage connected to the control input of said third transistor;

said second output of said second push-pull input stage connected to the first output of said third transistor, to the first output of said fourth transistor and to said inverted level converter output;

said second inputs of said first and second push-pull input stages and the second outputs of said first and third transistors connected to a first potential;

the second outputs of said second and fourth transistors connected to a second potential; and

the control input of said second transistor connected to said inverted level converter output, and the control input of said fourth transistor connected to said level converter output.

2. The level converter according to claim 1, wherein:

each of said push-pull input stages includes two transistors each having outputs and a control input;

the control inputs of said two transistors are connected to one another and to said second input of said push-pull input stage;

one of the outputs of each of said two transistors are connected in series and form said first output of said push-pull input stage;

another output of one of said two transistors forms said second output of said push-pull input stage; and

a further output of one of said two transistors forms said first input of said push-pull input stage.

3. The level converter according to claim 1, wherein said transistors are field-effect transistors.

4. The level converter according to claim 2, wherein said transistors are field-effect transistors.

5. The level converter according to claim 2, wherein one of said two transistors of each of said push-pull input stages is a p-channel transistor, and the other of said two transistors of each of said push-pull input stages is an n-channel transistor.

6. The level converter according to claim 1, wherein said first, second, third and fourth transistors are p-channel transistors.

7. The level converter according to claim 1, wherein said inverter is dimensioned asymmetrically for driving said push-pull input stages symmetrically.

8. The level converter according to claim 2, wherein said transistors have gate-source, gate-drain and drain-source voltages at least as low as the first potential.