Silicon on insulator domino logic circuits

• US 6,049,230 A
• Filed: 03/06/1998
• Issued: 04/11/2000
• Est. Priority Date: 03/06/1998
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Klim, Peter Gursen, Durham, Christopher McCall, Patel, Binta Minesh
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): Le, Don Phu
• Application Number:
  US09/036,448
• Time in Patent Office: 767 Days
• Field of Search: 326/93, 326/95, 326/112, 326/119, 326/121, 326/98, 326/81, 326/82, 327/534, 327/535
• US Class Current: 326/98
• CPC Class Codes: H03K 19/0963 using transistors of complementary type H03K19/0966 takes precedence

Abstract

A domino logic circuit having a clocked precharge is disclosed. The domino logic circuit includes a precharge transistor, a discharge transistor, multiple input transistors, and a supplemental precharge transistor. Connected to a power supply, the precharge transistor receives a clock input. The discharge transistor is connected to ground and also receives the clock input. The input transistors, which are coupled between the precharge transistor and the discharge transistor, each receives a signal input. The supplemental precharge transistor is connected to the power supply and to a body of each of the input transistors. The supplemental precharge transistor also receives the same clock input as the precharge transistor.

Claims

1. A domino logic circuit, comprising:

a precharge transistor connected to a power supply, wherein said precharge transistor receives a clock input;

at least one input transistor coupled to said precharge transistor, wherein said at least one input transistor receives a signal input; and

a supplemental precharge transistor connected to said power supply and to a body of said at least one input transistor, wherein said supplemental precharge transistor also receives said clock input.

2. The domino logic circuit according to claim 1, wherein said domino logic circuit is fabricated by silicon on insulator processing technology.

3. The domino logic circuit according to claim 1, wherein said precharge transistor and said supplemental precharge transistor are p-channel transistors while said one or more input transistors are n-channel transistors.

4. The domino logic circuit according to claim 1, wherein said domino logic circuit further includes an n-channel discharge transistor connected to ground, wherein said discharge transistor receives said clock input.

5. The domino logic circuit according to claim 1, wherein said domino logic circuit further includes an inverter.

6. The domino logic circuit according to claim 5, wherein said inverter includes a p-channel transistor and an n-channel transistor connected in series.

7. The domino logic circuit according to claim 5, wherein said domino logic circuit further includes a second supplement precharge transistor connected to said power supply and to a body of some of said at least one input transistors.

8. A domino logic circuit, comprising:

a precharge transistor for receiving a clock input, said precharge transistor having a source connected to a power supply;

a discharge transistor for receiving said clock input, wherein said discharge transistor having a source connected to ground;

a plurality of input transistors coupled between a drain of said precharge transistor and a drain of said discharge transistor, wherein each of said plurality of input transistors receives a signal input; and

a supplemental precharge transistor having a source connected to said power supply and a drain connected to a body of each of said plurality input transistors, wherein said supplemental precharge transistor also receives said clock input.

9. The domino logic circuit according to claim 8, wherein said domino logic circuit is fabricated by silicon on insulator processing technology.

10. The domino logic circuit according to claim 8, wherein said precharge transistor and said supplemental precharge transistor are p-channel transistors while said one or more input transistors and said discharge transistor are n-channel transistors.

11. The domino logic circuit according to claim 8, wherein said domino logic circuit further includes an inverter.

12. The domino logic circuit according to claim 11, wherein said inverter includes a p-channel transistor and an n-channel transistor connected in series.

13. The domino logic circuit according to claim 11, wherein said domino logic circuit further includes a second supplement precharge transistor connected to said power supply and to a body of some of said plurality of input transistors.

14. A domino logic circuit, comprising:

a precharge transistor connected to a power supply, wherein said precharge transistor receives a clock input;

a discharge transistor connected to ground, wherein said discharge transistor receives said clock input;

one or more input transistors coupled between said precharge transistor and said discharge transistor, wherein each of said one or more input transistors receives a signal input; and

a plurality of supplemental precharge transistors connected to said power supply, wherein each of said plurality of supplemental precharge transistors is connected to a body of a group of said one or more input transistors, wherein said supplemental precharge transistor also receives said clock input.

15. The domino logic circuit according to claim 14, wherein said domino logic circuit is fabricated by silicon on insulator processing technology.

16. The domino logic circuit according to claim 14, wherein said precharge transistor and said supplemental precharge transistor are p-channel transistors while said one or more input transistors and said discharge transistor are n-channel transistors.

17. The domino logic circuit according to claim 14, wherein said domino logic circuit further includes an inverter.

18. The domino logic circuit according to claim 17, wherein said inverter includes a p-channel transistor and an n-channel transistor connected in series.