Package with reticulated bond shelf

• US 6,049,470 A
• Filed: 01/13/1998
• Issued: 04/11/2000
• Est. Priority Date: 05/30/1997
• Status: Expired due to Term

• Current Assignee: Teledyne Dalsa Incorporated (Teledyne Technologies Incorporated)
• Original Assignee: Dalsa Incorporated (Teledyne Technologies Incorporated)
• Inventors: Weale, Gareth P.
• Primary Examiner(s): Picard, Leo P.
• Assistant Examiner(s): FOSTER, DAVID A
• Application Number:
  US09/006,662
• Time in Patent Office: 819 Days
• Field of Search: 361/820, 361/821, 361/826, 361/825, 361/829, 361/760, 361/764, 361/765, 361/766, 361/782, 361/783, 361/719, 361/720, 257/676, 257/668, 257/691, 257/723, 257/775, 257/776, 257/696, 257/724, 338/252, 338/272
• US Class Current: 361/820
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48175 the item being metallic
• CPC Class Codes: H01L 2224/48195 the item being a discrete passive component
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/4911 the connectors being bonded to at least one common bonding area, e.g. daisy chain
• CPC Class Codes: H01L 2224/49112 the connectors connecting a common bonding area on the semiconductor or solid-state body to different bonding areas outside the body, e.g. diverging wires
• CPC Class Codes: H01L 2224/92247 the second connecting process involving a wire connector
• CPC Class Codes: H01L 23/04 characterised by the shape of the container or parts, e.g. caps, walls
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/00015 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed as prior art
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01021 Scandium [Sc]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01074 Tungsten [W]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/1304 : Transistor
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/16195 : Flat cap [not enclosing an internal cavity]
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate

Abstract

A component package includes a case with a bond shelf and a conductive layer formed on the bond shelf. The bond shelf is characterized by an inward edge and an outward edge and at least one reticulation, each reticulation being characterized by an outward edge and an inward edge. The reticulation inward edge is co-linear with the bond shelf inward edge. The conductive layer includes a mounting pad for each reticulation and a serpentine conductor connecting the mounting pads, the mounting pad being disposed between the inward edge of the reticulation and the outward edge of the reticulation. The component package further includes a chip transistor mounted on a first mounting pad and a chip resistor mounted in a first reticulation. A semiconductor circuit mounted in the component package includes a bonding pad connected to a pad on the chip transistor and one end of the chip resistor.

Claims

1. A component comprising:

a case with a bond shelf, the bond shelf being characterized by an inward edge and an outward edge and at least one reticulation, each reticulation being characterized by an outward edge and an inward edge, the reticulation inward edge being co-linear with the bond shelf inward edge; and

a conductive layer formed on the bond shelf, the conductive layer including a mounting pad for each reticulation and a serpentine conductor connecting the mounting pads, the mounting pad being disposed between the inward edge of the reticulation and the outward edge of the reticulation.

2. The component of claim 1, further comprising a chip transistor mounted on a first mounting pad.

3. The component of claim 2, wherein the serpentine conductor includes a first portion disposed between the outward edge of the bond shelf and the outward edge of the reticulation.

4. The component of claim 3, further comprising a plurality of leads, each lead having a first end disposed between the inward edge of the reticulation and the outward edge of the reticulation.

5. The component of claim 1, wherein the serpentine conductor includes a first portion disposed between the outward edge of the bond shelf and the outward edge of the reticulation.

6. The component of claim 5, further comprising a plurality of leads, each lead having a first end disposed between the inward edge of the reticulation and the outward edge of the reticulation.

7. The component of claim 1, further comprising a plurality of leads, each lead having a first end disposed between the inward edge of the reticulation and the outward edge of the reticulation.

8. The component of claim 7, further comprising a chip transistor mounted on a first mounting pad, the chip transistor being connected to a lead of the plurality of leads.

9. The component of claim 1, wherein the case includes a cavity having a bottom, the component further comprising:

an integrated circuit mounted on the cavity bottom, the integrated circuit including an output pad;

a chip resistor disposed in a first reticulation, the chip resistor including a first end;

a chip transistor mounting on a first mounting pad, the chip transitor including an input pad and an output pad; and

a first bonding wire connecting the integrated circuit output pad to the chip transistor input pad and to the first end of the chip resistor.

10. The component of claim 9, further comprising:

a plurality of leads, each lead having a first end disposed between the inward edge of the reticulation and the outward edge of the reticulation; and

a second bonding wire connecting the chip transistor output pad to the first end of a first lead.

11. A method of manufacturing a component comprising steps of:

forming a case with a bond shelf, the bond shelf being characterized by an inward edge and an outward edge and at least one reticulation, each reticulation being characterized by an outward edge and an inward edge, the reticulation inward edge being co-linear with the bond shelf inward edge; and

forming a conductive layer on the bond shelf, the conductive layer including a mounting pad for each reticulation and a serpentine conductor connecting the mounting pads, the mounting pad being disposed between the inward edge of the reticulation and the outward edge of the reticulation.

12. The method of claim 11, further comprising a step of mounting a chip transistor on a first mounting pad.

13. The method of claim 12, wherein the step of forming a conductive layer forms the serpentine conductor to include a first portion disposed between the outward edge of the bond shelf and the outward edge of the reticulation.

14. The method of claim 13, further comprising a step of forming a plurality of leads integral with the case, each lead having a first end disposed between the inward edge of the reticulation and the outward edge of the reticulation.

15. The method of claim 11, wherein the step of forming a conductive layer forms the serpentine conductor to include a first portion disposed between the outward edge of the bond shelf and the outward edge of the reticulation.

16. The method of claim 15, further comprising a step of forming a plurality of leads integral with the case, each lead having a first end disposed between the inward edge of the reticulation and the outward edge of the reticulation.

17. The method of claim 11, further comprising a step of forming a plurality of leads integral with the case, each lead having a first end disposed between the inward edge of the reticulation and the outward edge of the reticulation.

18. The method of claim 17, further comprising a step of mounting a chip transistor on a first mounting pad, the chip transistor being connected to a lead of the plurality of leads.

19. The method of claim 11, wherein the step of forming the case includes forming a case cavity having a bottom, the method further comprising steps of:

mounting an integrated circuit on the cavity bottom, the integrated circuit including an output pad;

mounting a chip resistor in a first reticulation, the chip resistor including a first end;

mounting a chip transistor on a first mounting pad, the chip transitor including an input pad and an output pad; and

connecting a first bonding wire from the integrated circuit output pad to the chip transistor input pad and to the first end of the chip resistor.

20. The method of claim 19, further comprising steps of:

forming a plurality of leads integral with the case, each lead having a first end disposed between the inward edge of the reticulation and the outward edge of the reticulation; and

connecting a second bonding wire from the chip transistor output pad to the first end of a first lead.