High memory capacity DIMM with data and state memory

• US 6,049,476 A
• Filed: 07/31/1998
• Issued: 04/11/2000
• Est. Priority Date: 05/15/1995
• Status: Expired due to Term

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Silicon Graphics Incorporated (Graphics Properties Holdings, Inc.)
• Inventors: Anderson, Michael E., Manton, John, Lenoski, Daniel E., Laudon, James P.
• Primary Examiner(s): Hoang, Huan
• Application Number:
  US09/126,944
• Time in Patent Office: 620 Days
• Field of Search: 365/52, 365/63, 365/233, 365/51, 365/72, 365/230.03
• US Class Current: 365/52
• CPC Class Codes: G11C 5/00 Details of stores covered by group G11C11/00
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports

Abstract

A high memory capacity dual in-line memory module (DIMM) for use in a directory-based, distributed shared memory multiprocessor computer system including a data memory for storing data and a state memory for storing state or directory information corresponding to at least a portion of the data. The DIMM allows the data and the state information to be accessed independently. The DIMM can be configured in a plurality of storage capacities.

Claims

1. A dual in-line memory module (DIMM) comprising:

a circuit board; and

a plurality of semiconductor memory chips mounted on said circuit board, said memory chips being logically organized into a first memory bank portion and a second memory bank portion,

wherein said first and second memory bank portions are separately addressable,

wherein said first memory bank portion is logically organized into memory blocks for storing data, and wherein said second memory bank portion is configured to store directory information for said memory blocks of said first memory bank portion, and

wherein said plurality of semiconductor memory chips provide 128M of data storage on the DIMM.

2. The DIMM of claim 1, wherein said memory chips are selected from the group consisting of sixteen megabit by four bit (16M×

4), eight megabit by eight bit (8M×

8), four megabit by 16 bit (4M×

16) SDRAM chips and any combination thereof.

3. A pair of dual in-line memory modules (DIMMs), each DIMM comprising:

a circuit board; and

a plurality of semiconductor memory chips mounted on said circuit board, said memory chips being logically organized into a first memory bank portion and a second memory bank portion,

wherein said first and second memory bank portions are separately addressable,

wherein said first memory bank portion is logically organized into memory blocks for storing data, and wherein said second memory bank portion is configured to store directory information for said memory blocks of said first memory bank portion, and

wherein said plurality of semiconductor memory chips provide 256M of data storage on the DIMM pair.

4. The DIMM of claim 3, wherein said memory chips are selected from the group consisting of sixteen megabit by four bit (16M×

4), eight megabit by eight bit (8M×

8), four megabit by 16 bit (4M×

16) SDRAM chips and any combination thereof.

5. A piggyback dual in-line memory module (DIMM) comprising:

a circuit board having a piggyback board mounted thereon; and

a plurality of semiconductor memory chips mounted on said circuit board and said piggyback board, said memory chips being logically organized into a first memory bank portion and a second memory bank portion,

wherein said first and second memory bank portions are separately addressable,

wherein said first memory bank portion is logically organized into memory blocks for storing data, and wherein said second memory bank portion is configured to store directory information for said memory blocks of said first memory bank portion, and

wherein said plurality of semiconductor memory chips provide 256M of data storage on the piggyback DIMM.

6. The DIMM of claim 5, wherein said memory chips are selected from the group consisting of sixteen megabit by four bit (16M×

4), eight megabit by eight bit (8M×

8), four megabit by 16 bit (4M×

16) SDRAM chips and any combination thereof.

7. A pair of piggyback dual in-line memory modules (DIMMs), each DIMM comprising:

a circuit board having a piggyback board mounted thereon; and

a plurality of semiconductor memory chips mounted on said circuit board and said piggyback board, said memory chips being logically organized into a first memory bank portion and a second memory bank portion,

wherein said first and second memory bank portions are separately addressable,

wherein said first memory bank portion is logically organized into memory blocks for storing data, and wherein said second memory bank portion is configured to store directory information for said memory blocks of said first memory bank portion, and

wherein said plurality of semiconductor memory chips provide 512M of data storage on the piggyback DIMM pair.

8. The DIMM of claim 7, wherein said memory chips are selected from the group consisting of thirty-two megabit by four bit (32M×

4), sixteen megabit by eight bit (16M×

8), eight megabit by sixteen bit (8M×

16) SDRAM chips and any combination thereof.