Multiple-valued mask programmable read only memory semiconductor device with improved word level generator

• US 6,049,481 A
• Filed: 06/30/1998
• Issued: 04/11/2000
• Est. Priority Date: 06/30/1997
• Status: Expired due to Fees

• Current Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Original Assignee: NEC Corporation
• Inventors: Yamasaki, Kazuyuki
• Primary Examiner(s): NGUYEN, TAN
• Application Number:
  US09/107,462
• Time in Patent Office: 651 Days
• Field of Search: 365/185.03, 365/185.23, 365/189.29, 365/230.06, 365/94, 365/203, 365/204
• US Class Current: 365/185.23
• CPC Class Codes: G11C 17/08 using semiconductor devices, e.g. bipolar elements G11C17/06, G11C17/14 take precedence

Abstract

A word level generator in a multiple-valued mask programmable read only memory semiconductor device having a plurality of kinds of mask programmable read only memory cells having a plurality of distributions in number of the mask programmable read only memory cells versus variation of actual threshold voltages from predetermined threshold voltages. The distributions are separated from each other and do not overlap each other. The word level generator generates a word level which is between a maximum voltage level of lower one of adjacent two of the distributions and a minimum voltage level of higher one of the adjacent two of the distributions, so that all of the mask programmable read only memory cells are permitted to show correct ON/OFF operations for application of different word level voltages, whereby only correct data are obtained from the multiple-valued mask programmable read only memory semiconductor device.

Claims

1. A word level generator in a multiple-valued mask programmable read only memory semiconductor device having a plurality of kinds of mask programmable read only memory cells having a plurality of distributions in number of the mask programmable read only memory cells versus variation of actual threshold voltages from predetermined threshold voltages, and the distributions being separated from each other and having no overlap to each other,

wherein the word level generator generates signals corresponding to a maximum voltage level of a lower one of an adjacent two of the distributions and a minimum voltage level of a higher one of the adjacent two of the distributions and generates a word level between the maximum and minimum voltage levels.

2. The word level generator as claimed in claim 1, wherein the word level generator comprises.

a first reference level generator circuit having a transistor with the same structure as the first kind of a mask programmable read only memory cells for generating a first reference level signal;

a second reference level generator circuit having a transistor with the same structure as the second kind of a mask programmable read only memory cells for generating a second reference level signal; and

a word level generator circuit connected to the first and second reference level generator circuits for receiving the first and second reference level signals from the first and second reference level generator circuits in order to generate a word level intermediate between the first and second reference level signals.

3. The word level generator as claimed in claim 1, wherein a plurality of the word level generator circuits are provided for individually generating different word levels which lie in individual intermediate ranges between adjacent pairs of the distributions.

4. A word level generator for a multi-valued programmable read only semiconductor memory device that has plural kinds of programmable read only memory cells, each of the plural kinds of cells having a distribution of a number of such cells versus a variation of actual threshold voltage from a defined threshold voltage, the distributions being separate from each other so that a maximum voltage value of a lower one of an adjacent pair of the distributions does not overlap a minimum voltage value of a minimum voltage of a higher one of the adjacent pair, the word level generator comprising:

a first reference level generator circuit for generating a first reference level which corresponds to the maximum value of the lower distribution;

a second reference level generator circuit for generating a second reference level which corresponds to the minimum value of the higher distribution; and

a word level generator circuit connected to the first and second reference level generator circuits for receiving the first and second reference levels from the first and second reference level generator circuits and for generating the word level which lies between the first and second reference levels.

5. The word level generator as claimed in claim 4, wherein the word level generator circuit generates a word level which is an intermediate level between the first and second reference levels.

6. The word level generator as claimed in claim 4, wherein the word level generator circuit comprises:

a voltage-divider circuit connected to the first and second reference level generator circuits for receiving the first and second reference levels to generate a voltage at a level between the first and second reference levels; and

a current-amplifier circuit connected to the voltage-divider circuit for receiving the output from the voltage-divider circuit to conduct an amplification in current of the output from the voltage-divider circuit.

7. The word level generator as claimed in claim 6, wherein the first reference level generator circuit comprises:

a first reference level generator circuit for generating the first reference level; and

a first current amplifier circuit connected to the first reference level generator circuit for receiving the first reference level from the first reference level generator circuit in order to conduct a current amplification of the first reference level, and

wherein the second reference level generator circuit comprises;

a second reference level generator circuit for generating the second reference level; and

a second current amplifier circuit connected to the second reference level generator circuit for receiving the second reference level from the second reference level generator circuit in order to conduct a current amplification of the second reference level.

8. The word level generator as claimed in claim 7, wherein the first reference level generator circuit has at least a first MOS field effect transistor having a first threshold voltage which corresponds to the first reference level, and wherein the second reference level generator circuit has at least a second MOS field effect transistor having a second threshold voltage which corresponds to the second reference level.

9. The word level generator as claimed in claim 8, wherein each of the first and second MOS field effect transistors has a diode connection between a drain and a gate to allow the first and second MOS field effect transistors to perform as diodes so that a drain voltage of the first MOS field effect transistor is fetched as the first reference level signal and a drain voltage of the second MOS field effect transistor is fetched as the second reference level.

10. The word level generator as claimed in claim 8, wherein the first reference level generator circuit further has a first set of peripheral MOS field effect transistors provided adjacent to and around the first MOS field effect transistor, where the first MOS field effect transistor has an impurity diffusion region having the same amount of impurity as an impurity diffusion region of a mask programmable read only memory cell which has a threshold voltage equal to a first predetermined threshold voltage from which actual threshold voltages of the first kind of the mask programmable read only memory cells are varied with the lower distribution, whilst the first set of the peripheral MOS field effect transistors have impurity diffusion regions having the same amount of impurity as an impurity diffusion region of a mask programmable read only memory cell which has a predetermined threshold voltage belonging to a highest one of all the distributions, and

wherein the second reference level generator circuit further has a second set of peripheral MOS field effect transistors provided adjacent to and around the second MOS field effect transistor, where the second MOS field effect transistor has an impurity diffusion region having the same amount of impurity as an impurity diffusion region of a mask programmable read only memory cell which has a threshold voltage equal to a second predetermined threshold voltage from which actual threshold voltages of the second kind of the mask programmable read only memory cells are varied with the higher distribution, whilst the second set of the peripheral MOS field effect transistors have impurity diffusion regions having the same amount of impurity as an impurity diffusion region of a mask programmable read only memory cell which a predetermined threshold voltage belonging to a lowest one of all the distributions.

11. A device for generating a word level that is both higher than a maximum voltage value of a first distribution in threshold voltage of first type mask programmable read only memory cells intended to have a first threshold voltage and lower than a minimum voltage value of a second distribution in threshold voltage of second type mask programmable read only memory cells intended to have a second threshold voltage, the first and second distributions being adjacent to each other and separated from each other to have no overlap so that the first distribution is lower in threshold voltage than the second distribution,

the device comprising means for generating signals corresponding to the maximum and minimum voltage values and for generating the word level therebetween using the corresponding signals.

12. The device as claimed in claim 11, wherein the means for generating comprises:

a first reference level generator circuit having a transistor with the same structure as the first type of the mask programmable read only memory cells for generating a first reference level signal;

a second reference level generator circuit having a transistor with the same structure as the second type of the mask programmable read only memory cells for generating a second reference level signal; and

a word level generator connected to the first and second reference level generator circuits for receiving the first and second reference level signals from the first and second reference level generator circuits in order to generate a word level intermediate between the first and second reference level signals.

13. The device as claimed in claim 11, wherein a plurality of said means for generating are provided for individually generating different word levels which lie in individual intermediate ranges between adjacent pairs of the distributions.

14. A device for generating a word level that is both higher than a maximum voltage value of a first distribution in threshold voltage of first type mask programmable read only memory cells intended to have a first threshold voltage and lower than a minimum voltage value of a second distribution in threshold voltage of second type mask programmable read only memory cells intended to have a second threshold voltage, the first and second distributions being adjacent to each other and separated from each other to have no overlap so that the first distribution is lower in threshold voltage than the second distribution, the device comprising:

a first reference level generator circuit for generating a first reference level which corresponds to the maximum value of the first distribution;

a second reference level generator circuit for generating a second reference level which corresponds to the minimum value of the second distribution; and

a word level generator connected to the first and second reference level generator circuits for receiving the first and second reference levels from the first and second reference level generator circuits and for generating the word level which lies between the first and second reference levels.

15. The device as claimed in claim 14, wherein the word level generator generates a word level which is an intermediate level between the first and second reference levels.

16. The device as claimed in claim 14, wherein the word level generator comprises:

a voltage-divider circuit connected to the first and second reference level generator circuits for receiving the first and second reference levels to generate a voltage at a level between the first and second reference levels; and

a current-amplifier circuit connected to the voltage-divider circuit for receiving the output from the voltage-divider circuit to conduct an amplification in current of the output from the voltage-divider circuit.

17. The device as claimed in claim 16, wherein the first reference level generator circuit comprises:

a first reference level generator circuit for generating the first reference level; and

a first current amplifier circuit connected to the first reference level generator circuit for receiving the first reference level from the first reference level generator circuit in order to conduct a current amplification of the first reference level, and

wherein the second reference level generator circuit comprises;

a second reference level generator circuit for generating the second reference level; and

a second current amplifier circuit connected to the second reference level generator circuit for receiving the second reference level from the second reference level generator circuit in order to conduct a current amplification of the second reference level.

18. The device as claimed in claim 17, wherein the first reference level generator circuit has at least a first MOS field effect transistor having a first threshold voltage which corresponds to the first reference level, and wherein the second reference level generator circuit has at least a second MOS field effect transistor having a second threshold voltage which corresponds to the second reference level.

19. The device as claimed in claim 18, wherein each of the first and second MOS field effect transistors has a diode connection between a drain and a gate to allow the first and second MOS field effect transistors to perform as diodes so that a drain voltage of the first MOS field effect transistor is fetched as the first reference level and a drain voltage of the second MOS field effect transistor is fetched as the second reference level.

20. The device as claimed in claim 18, wherein the first reference level generator circuit further has a first set of peripheral MOS field effect transistors provided adjacent to and around the first MOS field effect transistor, where the first MOS field effect transistor has an impurity diffusion region having the same amount of impurity as an impurity diffusion region of a mask programmable read only memory cell which has a threshold voltage equal to a first predetermined threshold voltage from which actual threshold voltages of the first kind of the mask programmable read only memory cells are varied with the first distribution, whilst the first set of the peripheral MOS field effect transistors have impurity diffusion regions having the same amount of impurity as an impurity diffusion region of a mask programmable read only memory cell which has a predetermined threshold voltage belonging to a highest one of all the distributions, and

wherein the second reference level generator circuit further has a second set of peripheral MOS field effect transistors provided adjacent to and around the second MOS field effect transistor, where the second MOS field effect transistor has an impurity diffusion region having the same amount of impurity as an impurity diffusion region of a mask programmable read only memory cell which has a threshold voltage equal to a second predetermined threshold voltage from which actual threshold voltages of the second kind of the mask programmable read only memory cells are varied with the second distribution, whilst the second set of the peripheral MOS field effect transistors have impurity diffusion regions having the same amount of impurity as an impurity diffusion region of a mask programmable read only memory cell which a predetermined threshold voltage belonging to a lowest one of all the distributions.

21. A multiple-valued mask programmable read only memory semiconductor device comprising:

a memory cell array including a plurality of kinds of mask programmable read only memory cells having a plurality of distributions in number of the mask programmable read only memory cells versus variation of actual threshold voltages from predetermined threshold voltages, and the distributions being separated from each other and having no overlap to each other;

a sense amplifier connected to the mask programmable read only memory cells for sensing ON/OFF states of said mask programmable read only memory cells;

a plurality of latch circuits connected to the sense amplifier for receiving output signals about the ON/OFF states from said sense amplifier to hold the output signals;

a decoder circuit connected to the latch circuits for receiving the output signals from the latch circuits to decode the output signals into data about the ON/OFF states;

a plurality of output buffer circuits connected to the decoder circuit for outputting the data about the ON/OFF states; and

a word level generator connected to gates of the mask programmable read only memory cells for supplying at least one word level for controlling ON/OFF states of said mask programmable read only memory cells,

wherein the word level generator generates voltages corresponding to a maximum voltage level of a lower one of an adjacent two of the distributions and a minimum voltage level of a higher one of the adjacent two of the distributions and generates a word level between the maximum and minimum voltage levels.

22. The multiple-valued mask programmable read only memory semiconductor device as claimed in claim 21, wherein the word level generator comprises:

a first reference level generator circuit having a transistor with the same structure as a first kind of the mask programmable read only memory cells for generating a first reference level signal;

a second reference level generator circuit having a transistor with the same structure as a second kind of the mask programmable read only memory cells for generating a second reference level signal; and

a word level generator circuit connected to the first and second reference level generator circuits for receiving the first and second reference level signals from the first and second reference level generator circuits in order to generate a word level intermediate between the first and second reference levels.

23. The multiple-valued mask programmable read only memory semiconductor device as claimed in claim 21, wherein a plurality of the word level generator circuits are provided for individually generating different word levels which lie in individual intermediate ranges between adjacent pairs of the distributions.

24. A multiple-valued mask programmable read only memory semiconductor device comprising:

a memory cell array including a plurality of kinds of mask programmable read only memory cells having a plurality of distributions in number of the mask programmable read only memory cells versus variation of actual threshold voltages from predetermined threshold voltages, and the distributions being separated from each other and having no overlap to each other;

a sense amplifier connected to the mask programmable read only memory cells for sensing ON/OFF states of said mask programmable read only memory cells;

a plurality of latch circuits connected to the sense amplifier for receiving output signals about the ON/OFF states from said sense amplifier to hold the output signals;

a decoder circuit connected to the latch circuits for receiving the output signals from the latch circuits to decode the output signals into data about the ON/OFF states;

a plurality of output buffer circuits connected to the decoder circuit for outputting the data about the ON/OFF states; and

a word level generator connected to gates of the mask programmable read only memory cells for supplying at least one word level for controlling ON/OFF states of said mask programmable read only memory cells,

wherein the word level generator generates voltages corresponding to a maximum voltage level of a lower one of an adjacent two of the distributions and a minimum voltage level of a higher one of the adjacent two of the distributions and generates a word level between the maximum and minimum voltage levels,

wherein the word level generator comprises,

a first reference level generator circuit for generating a first reference level which corresponds to the maximum value of the lower distribution,

a second reference level generator circuit for generating a second reference level which corresponds to the minimum value of the higher distribution, and

a word level generator circuit connected to the first and second reference level generator circuits for receiving the first and second reference levels from the first and second reference level generator circuits in order to generate the word level which lies between the first and second reference levels.

25. The multiple-valued mask programmable read only memory semiconductor device as claimed in claim 24, wherein the word level generator circuit generates a word level which is an intermediate level between the first and second reference levels.

26. The multiple-valued mask programmable read only memory semiconductor device as claimed in claim 24, wherein the word level generator circuit comprises:

a voltage-divider circuit connected to the first and second reference level generator circuits for receiving the first and second reference levels to generate a voltage at a level between the first and second reference levels; and

a current-amplifier circuit connected to the voltage-divider circuit for receiving the output from the voltage-divider circuit to conduct an amplification in current of the output from the voltage-divider circuit.

27. The multiple-valued mask programmable read only memory semiconductor device as claimed in claim 26, wherein the first reference level generator circuit comprises:

a first reference level generator circuit for generating the first reference level; and

a first current amplifier circuit connected to the first reference level generator circuit for receiving the first reference level from the first reference level generator circuit in order to conduct a current amplification of the first reference level, and

wherein the second reference level generator circuit comprises;

a second reference level generator circuit for generating the second reference level; and

a second current amplifier circuit connected to the second reference level generator circuit for receiving the second reference level from the second reference level generator circuit in order to conduct a current amplification of the second reference level.

28. The multiple-valued mask programmable read only memory semiconductor device as claimed in claim 27, wherein the first reference level generator circuit has at least a first MOS field effect transistor having a first threshold voltage which corresponds to the first reference level, and wherein the second reference level generator circuit has at least a second MOS field effect transistor having a second threshold voltage which corresponds to the second reference level.

29. The multiple-valued mask programmable read only memory semiconductor device as claimed in claim 28, wherein each of the first and second MOS field effect transistors has a diode connection between a drain and a gate to allow the first and second MOS field effect transistors to perform as diodes so that a drain voltage of the first MOS field effect transistor is fetched as the first reference level and a drain voltage of the second MOS field effect transistor is fetched as the second reference level.

30. The multiple-valued mask programmable read only memory semiconductor device as claimed in claim 28, wherein the first reference level generator circuit further has a first set of peripheral MOS field effect transistors provided adjacent to and around the first MOS field effect transistor, where the first MOS field effect transistor has an impurity diffusion region having the same amount of impurity as an impurity diffusion region of a mask programmable read only memory cell which has a threshold voltage equal to a first predetermined threshold voltage from which actual threshold voltages of the first kind of the mask programmable read only memory cells are varied with the lower distribution, whilst the first set of the peripheral MOS field effect transistors have impurity diffusion regions having the same amount of impurity as an impurity diffusion region of a mask programmable read only memory cell which has a predetermined threshold voltage belonging to a highest one of all the distributions, and

wherein the second reference level generator circuit further has a second set of peripheral MOS field effect transistors provided adjacent to and around the second MOS field effect transistor, where the second MOS field effect transistor has an impurity diffusion region having the same amount of impurity as an impurity diffusion region of a mask programmable read only memory cell which has a threshold voltage equal to a second predetermined threshold voltage from which actual threshold voltages of the second kind of the mask programmable read only memory cells are varied with the higher distribution, whilst the second set of the peripheral MOS field effect transistors have impurity diffusion regions having the same amount of impurity as an impurity diffusion region of a mask programmable read only memory cell which a predetermined threshold voltage belonging to a lowest one of all the distributions.

31. A method of determining a word level that is both higher than a maximum voltage value of a first distribution in threshold voltage of first type mask programmable read only memory cells intended to have a first threshold voltage and lower than a minimum voltage value of a second distribution in threshold voltage of second type mask programmable read only memory cells intended to have a second threshold voltage, provided that the first and second distributions are separated from each other to have no overlap so that the first distribution is lower in threshold voltage than the second distribution,

the method comprising the steps of generating signals corresponding to the maximum and minimum voltage values, and generating the word level using the corresponding voltages.