Microprocessor with circuits, systems, and methods for operating with patch micro-operation codes and patch microinstruction codes stored in multi-purpose memory structure

• US 6,049,672 A
• Filed: 03/07/1997
• Issued: 04/11/2000
• Est. Priority Date: 03/08/1996
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Bosshart, Patrick W., Shiell, Jonathan H.
• Primary Examiner(s): Downs, Robert W.
• Application Number:
  US08/812,646
• Time in Patent Office: 1,131 Days
• Field of Search: 711/118-125, 711/102, 711/165, 395/182.01, 395/182.04, 395/385, 395/712
• US Class Current: 717/168
• CPC Class Codes: G06F 8/66 of program code stored in read-only memory [ROM]
• CPC Class Codes: G06F 9/268 Microinstruction selection not based on processing results, e.g. interrupt, patch, first cycle store, diagnostic programs
• CPC Class Codes: G06F 9/30003 Arrangements for executing specific machine instructions
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/3017 Runtime instruction translation, e.g. macros
• CPC Class Codes: G06F 9/328 for runtime instruction patching
• CPC Class Codes: G06F 9/382 Pipelined decoding, e.g. using predecoding
• CPC Class Codes: G06F 9/4494 data driven

Abstract

A microprocessor operates in response to microinstructions stored in a read only memory. A patch table stores a indication of patch microinstructions stored in cache memory. This cache memory caches data and/or macroinstructions for the microprocessor. Each new microaddress is compared with the patch table entries. If there in no match, then a multiplexer selects the microinstruction recalled from that microinstruction address within the microinstruction read only memory. If there is a match, then a corresponding patch microinstruction is recalled from the cache memory. The multiplexer selects this patch microinstruction. The microprocessor operates under the control of the selected microinstruction. This technique enables a fix of faulty microinstructions in the field, by supplying the computer user with the patch microinstructions. Using a portion of the cache memory to store the patch microinstructions eliminates any problem with specifying too large or too small a memory for patch microinstructions.

Claims

1. A processor disposed on a single integrated circuit operable in response to microinstructions, said processor comprising:

a microaddress sequencer generating a next microaddress;

a read only microinstruction memory circuit coupled to said microaddress sequencer, said microinstruction memory circuit storing a plurality of original microinstructions fixed upon manufacture at corresponding microaddresses and operable to output an original microinstruction stored at a microaddress received from said microaddress sequencer in response to a request signal;

a cache memory circuit simultaneously both caching a first type of information different from microinstructions and also storing at least one patch microinstruction, said cache memory circuit coupled to output at least said first type of information and to output a patch microinstruction in response to the request signal; and

selection circuitry coupled to said microinstruction memory circuit and said cache memory circuit for selecting for control of the processor for a next cycle between the original microinstruction recalled from said microinstruction memory circuit and the patch microinstruction recalled from said cache memory circuit.

2. The processor of claim 1:

wherein said selection circuitry comprises a patch memory table for storing a set of microaddresses;

wherein each microaddress of said set of microaddresses stored in said patch memory table corresponds to a patch microinstruction stored in said cache memory circuit; and

wherein said selection circuitry selects said original microinstruction when said next microaddress fails to match any of said set of microaddresses and selects said patch microinstruction when said next microaddress matches any of said set of microaddresses.

3. The processor of claim 2:

wherein said selection circuitry further comprises a multiplexer;

wherein said multiplexer has a first data input coupled to an output of said microinstruction memory circuit receiving said original microinstruction;

wherein said multiplexer has a second input coupled to an output of said cache circuit receiving said patch microinstruction; and

wherein said multiplexer has a control input coupled to receive a control signal from said patch memory table, said control input causing said multiplexer to select said first data input if said next microaddress fails to match any of said set of microaddresses stored in said patch memory table and to select said second data input if said next microaddress matches any of said set of microaddresses stored in said patch memory table.

4. The processor of claim 2 wherein said patch memory table comprises a random access memory, wherein said random access memory outputs a control signal in response to being addressed by said next microaddress, said control signal indicating whether said next microaddress is stored in said patch memory table, and wherein said selection circuitry selects in response to the control signal.

5. The processor of claim 2 wherein said patch memory table comprises a content addressable memory, wherein said set of microaddresses is stored in said content addressable memory such that said content addressable memory outputs a control signal in response to receiving said next microaddress, said control signal indicating whether said next microaddress is stored in said patch memory table, and wherein said selection circuitry selects in response to the control signal.

6. The processor of claim 1 and further comprising circuitry for writing the at least one patch microinstruction to a location in said cache memory circuit.

7. The processor of claim 6 and further comprising circuitry for preventing overwriting of the at least one patch microinstruction in the location.

8. The processor of claim 6 and further comprising circuitry for indicating that data stored in the location in said cache memory circuit comprises a patch microinstruction.

9. The processor of claim 1 wherein:

said first type information cached in said cache memory circuit includes data processed by the processor.

10. The processor of claim 1 wherein:

said first type information cached in said cache memory circuit includes macroinstructions employed the processor.

11. The processor of claim 1 wherein:

said first type information cached in said cache memory circuit includes data processed by the processor and macroinstructions employed by the processor.

12. A method of operating a microprocessor in response to an identified code, said method comprising the steps of:

storing in a read only microinstruction memory circuit a plurality of original microinstructions fixed upon manufacture at corresponding microaddresses;

issuing a request signal requesting a microinstruction from a next microaddress;

outputting an original microinstruction from a memory location within the microinstruction memory circuit corresponding to the next microaddress in response to the request signal;

simultaneously both caching a first type of information other than microinstructions in a cache memory circuit and also storing at least one patch microinstruction in respective locations in the cache memory circuit;

detecting whether the next microaddress of the request signal corresponds to at least one patch microinstruction;

in response to detecting that the next microaddress of the request signal corresponds to the at least one patch microinstruction, outputting the at least one patch microinstruction from cache memory circuit in response to the request signal; and

selecting for control of the microprocessor for a next cycle between the at least one original microinstruction recalled from the microinstruction memory circuit and the at least one patch microinstruction recalled from the cache memory circuit.

13. The method of claim 12 and further comprising the steps of:

storing in a patch memory table a set of microaddresses, each microaddress corresponding to one of the at least one patch microinstruction stored in the cache memory circuit; and

wherein said detecting step comprises coupling the microaddress to the patch memory table for detecting whether the microaddress matches any of the set of microaddresses.

14. The method of claim 13:

wherein said selecting step comprises operating a multiplexer to select between the at least one original microinstruction and the at least one patch microinstruction;

wherein said multiplexer has a first data input coupled to an output of said microinstruction memory circuit receiving said original microinstruction;

wherein said multiplexer has a second input coupled to an output of said cache memory circuit receiving said patch microinstruction; and

wherein said multiplexer has a control input coupled to receive a control signal from said patch memory table, said control input causing the multiplexer to select the first data input if the next microaddress fails to match any of the set of microaddresses stored in the patch memory table and to select the second data input if the next microaddress matches any of the set of microaddresses stored in the patch memory table.

15. The method of claim 13:

wherein said patch memory table comprises a random access memory, wherein said random access memory outputs a control signal in response to being addressed by said next microaddress, said control signal indicating whether said next microaddress is stored in said patch memory table, and wherein said selecting step comprises selecting in response to the control signal.

16. The method of claim 13 wherein said patch memory table comprises a content addressable memory, wherein said set of microaddresses is stored in said content addressable memory such that said content addressable memory outputs a control signal in response to receiving said next microaddress, said control signal indicating whether said next microaddress is stored in said patch memory table, and wherein said selecting step comprises selecting in response to the control signal.

17. The method of claim 12 and further comprising the step of indicating that data stored in the location in said cache memory circuit comprises a patch microinstruction.

18. The method of claim 12 wherein:

said first type information cached in said cache memory circuit includes data processed by the microprocessor.

19. The method of claim 12 wherein:

said first type information cached in said cache memory circuit includes macroinstructions employed the microprocessor.

20. The method of claim 12 wherein:

said first type information cached in said cache memory circuit includes data processed by the microprocessor and macroinstructions employed by the microprocessor.