Integrated circuit having memory which synchronously samples information with respect to external clock signals

• US 6,049,846 A
• Filed: 09/25/1998
• Issued: 04/11/2000
• Est. Priority Date: 04/18/1990
• Status: Expired due to Fees

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Horowitz, Mark, Farmwald, Michael
• Primary Examiner(s): AUVE, GLENN ALLEN
• Application Number:
  US09/161,090
• Time in Patent Office: 564 Days
• Field of Search: 710/126, 710/129, 713/400, 713/500, 713/600
• US Class Current: 710/305
• CPC Class Codes: G06F 11/006 Identification G06F11/2289 takes precedence
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 12/0215 with look ahead addressing means
• CPC Class Codes: G06F 12/0661 and decentralised selection
• CPC Class Codes: G06F 12/0684 with feedback, e.g. presence or absence of unit detected by addressing, overflow detection
• CPC Class Codes: G06F 13/1605 based on arbitration arbitration in handling access to a common bus or bus system G06F13/36
• CPC Class Codes: G06F 13/161 with latency improvement
• CPC Class Codes: G06F 13/1678 using bus width
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 13/376 using a contention resolving method, e.g. collision detection, collision avoidance
• CPC Class Codes: G06F 13/4239 with asynchronous protocol
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 2207/105 Aspects related to pads, pins or terminals
• CPC Class Codes: G11C 2207/108 Wide data ports
• CPC Class Codes: G11C 29/88 with partially good memories
• CPC Class Codes: G11C 5/00 Details of stores covered by group G11C11/00
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: G11C 5/063 : Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 5/066 : Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
• CPC Class Codes: G11C 7/1006 : Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1012 : Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
• CPC Class Codes: G11C 7/1045 : Read-write mode select circuits
• CPC Class Codes: G11C 7/1051 : Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1057 : Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/1066 : Output synchronization
• CPC Class Codes: G11C 7/1069 : I/O lines read out arrangements
• CPC Class Codes: G11C 7/1072 : for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/1078 : Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1084 : Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/22 : Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 : Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: G11C 7/225 : Clock input buffers
• CPC Class Codes: G11C 8/00 : Arrangements for selecting an address in a digital store for stores using transistors G11C11/407, G11C11/413
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A synchronous memory device having at least one memory section which includes a plurality of memory cells. The memory device includes clock receiver circuitry, clock generation circuitry and input receiver circuitry. The clock receiver circuitry receives an external clock signal from an external bus. The clock generation circuitry is coupled to the clock receiver circuitry, and includes a delay locked loop to generate a first internal clock signal. The input receiver circuitry is coupled to the clock generation circuitry and the external bus to sample information from the external bus in response to the first internal clock signal.

Claims

1. A synchronous memory device, wherein the memory device includes at least one memory section having a plurality of memory cells, the memory device comprising:

clock receiver circuitry to receive an external clock signal from an external bus;

clock generation circuitry coupled to the clock receiver circuitry, wherein the clock generation circuitry includes a delay locked loop to generate a first internal clock signal; and

input receiver circuitry, coupled to the clock generation circuitry and the external bus, to sample information from the external bus in response to the first internal clock signal.

2. The memory device of claim 1 wherein the information is included in a request packet.

3. The memory device of claim 1, wherein the clock generation circuit further generates a second internal clock signal which is synchronized with the external clock signal and the input receiver further includes:

a first input latch to sample first information synchronously with respect to an edge of the first internal clock signal; and

a second input latch to sample second information synchronously with respect to an edge of the second internal clock signal.

4. The memory device of claim 3, wherein the first and second internal clock signals are complementary signals.

5. The memory device of claim 1, further including:

second clock generation circuitry coupled to the clock receiver circuitry, wherein the second clock generation circuitry includes a delay locked loop to generate a second internal clock signal; and

wherein the input receiver circuitry includes;

a first input latch to sample first information synchronously with respect to a clock edge of the first internal clock signal; and

a second input latch to sample second information synchronously with respect to a clock edge of the second internal clock signal.

6. The memory device of claim 5 wherein the clock edge of the first internal clock signal is a rising edge transition and the clock edge of the second internal clock signal is a rising edge transition.

7. The memory device of claim 1 wherein the external clock signal has a low voltage swing and the first internal clock signal has a full logic swing.

8. An integrated circuit having at least one memory section including a plurality of memory cells, the integrated circuit comprising:

clock receiver circuitry to receive an external clock signal from an external bus;

clock generation circuitry coupled to clock receiver circuitry to receive the external clock signal and to generate a first internal clock signal and a second internal clock signal, wherein the clock generation circuitry includes a delay locked loop to generate the first internal clock signal; and

input receiver circuitry, coupled to the external bus and the clock generation circuitry, to sample information from the external bus in response to the first and second internal clock signals.

9. The integrated circuit of claim 8, wherein the input receiver circuitry includes:

a first input latch to latch first information synchronously with respect to an edge of the first internal clock signal; and

a second input latch to latch second information synchronously with respect to an edge of the second internal clock signal.

10. The integrated circuit of claim 9 wherein the first internal clock signal is complementary to the second internal clock signal, the edge of the first internal clock signal is a rising edge, and the edge of the second internal clock signal is a rising edge.

11. The integrated circuit of claim 9 wherein the first and second information are included in a request packet.

12. The integrated circuit of claim 11, wherein the first and second information are included in the same request packet.

13. The integrated circuit of claim 8 wherein the clock generation circuitry includes a second delay locked loop to generate the second internal clock signal.

14. A synchronous memory device having at least one memory section including a plurality of memory cells, the memory device comprising:

clock receiver circuitry to receive a first and a second external clock signal from an external bus; and

input receiver circuitry, coupled to the clock receiver circuitry and the external bus, to sample information on the external bus synchronously with respect to the first and second external clock signals.

15. The memory device of claim 14, further including:

a clock generation circuit, coupled to the clock receiver circuitry, to generate a first internal clock signal which is synchronized with the first and second external clock signals; and

wherein the input receiver circuitry samples information on the external bus in response to the first internal clock signal.

16. The memory device of claim 15 wherein the input receiver circuitry samples first information synchronously with respect to the first and second external clock signals and wherein the first information is included in a request packet.

17. The memory device of claim 15 wherein the clock generation circuit generates the first internal clock signal using a delay locked loop.

18. The memory device of claim 14, further including:

a clock generation circuit, coupled to the clock receiver circuitry, to generate first and second internal clock signal; and

wherein the input receiver circuitry samples first information on the external bus in response to the first internal clock signal and samples second information on the external bus in response to the second internal clock signal.

19. The memory device of claim 18 wherein the input receiver circuitry samples first information synchronously with respect to a rising edge of the first external clock signal and samples second information synchronously with respect to a falling edge of the first external clock signal.

20. The memory device of claim 18 wherein the input receiver further includes:

a first input latch coupled to the first internal clock signal, wherein the first input latch latches first information in response to a rising edge of the first internal clock signal; and

a second input latch coupled to the second internal clock signal, wherein the second input latch latches second information in response to a rising edge of the second internal clock signal.

21. The memory device of claim 20 wherein a clock transition edge of the second internal clock signal occurs between a rising edge of the first external clock signal and a rising edge of the second external clock signal, and the second internal clock signal is complementary to the first internal clock signal.

22. The memory device of claim 20 wherein the first internal clock signal is complementary to the second internal clock signal.

23. The memory device of claim 20 further including:

a first clock generation circuit, coupled to the clock receiver circuitry, to generate a first internal clock signal which is synchronized with the first external clock signal;

a second clock generation circuit, coupled to the clock receiver circuitry, to generate a second internal clock signal which is synchronized with the second external clock signal; and

wherein the input receiver further includes;

a first input latch to latch first information in response to a transition of the first internal clock signal; and

a second input latch to latch second information in response to a transition of the second internal clock signal.

24. The memory device of claim 23 wherein the transition of the first internal clock signal is a rising edge transition and the transition of the second internal clock signal is a rising edge transition.

25. The memory device of claim 23 wherein the first clock generation circuit includes a first delay locked loop, and the second clock generation circuit includes a second delay locked loop.

26. An integrated circuit having at least one memory section including a plurality of memory cells, the integrated circuit comprising:

clock receive circuitry to receive a first and second external clock signal from a bus;

clock generation circuitry, coupled to the clock receiver circuitry, to generate first and second internal clock signals synchronized with the first and second external clock signals; and

input receiver circuitry, coupled to the bus, to sample information from the bus synchronously with respect to the first and second external clock signals.

27. The integrated circuit of claim 26, wherein the input receiver circuitry includes:

a first input latch coupled to the bus, wherein the first input latch latches first information synchronously in response to a first transition of the first external clock signal; and

a second input latch coupled to the bus, wherein the second input latch latches second information synchronously with respect to a second transition of the first external clock signal.

28. The integrated circuit of claim 27 wherein the first transition is a low-voltage swing rising edge and the second transition is a low-voltage swing falling edge.

29. The integrated circuit of claim 26 wherein the input receiver circuitry includes first and second input latches coupled to the bus, and wherein the first input latch latches first information in response to a rising edge transition of the first internal clock signal, and the second input latch latches second information in response to a rising edge transition of the second internal clock signal.

30. The integrated circuit of claim 26 wherein the first and second information are included in a request packet.

31. The integrated circuit of claim 26 wherein the first and second information are included in the same request packet.

32. The integrated circuit of claim 26 wherein the clock generation circuit generates the first internal clock signal using a delay locked loop, and wherein the input receiver circuitry samples the information in response to the first internal clock signal.

33. The integrated circuit of claim 26 wherein a clock transition edge of the first internal clock signal occurs between a rising edge of the first external clock signal and a rising edge of the second external clock signal, and a clock transition edge of the second internal clock signal occurs between a rising edge of the first external clock signal and a rising edge of the second external clock signal.