Method for scheduling a flag generating instruction and a subsequent instruction by executing the flag generating instruction in a microprocessor

• US 6,049,864 A
• Filed: 08/20/1996
• Issued: 04/11/2000
• Est. Priority Date: 08/20/1996
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Pai, Anand, Yellamilli, Krishna, Shoemaker, Ken, Liu, Kin-Yip, Hammond, Gary
• Primary Examiner(s): Maung, Zarni
• Assistant Examiner(s): Barot, Bharat
• Application Number:
  US08/699,910
• Time in Patent Office: 1,330 Days
• Field of Search: 395/376-394, 395/561, 395/564, 395/566, 395/567, 395/800.23, 395/800.41, 395/800.42, 395/800.32, 712/200, 712/214-216, 712/220-221, 712/223, 712/226, 712/245, 712/23, 712/32, 712/41
• US Class Current: 712/214
• CPC Class Codes: G06F 9/30094 Condition code generation, e.g. Carry, Zero flag
• CPC Class Codes: G06F 9/30174 for non-native instruction set, e.g. Javabyte, legacy code

Abstract

A method for scheduling a flag generating instruction and a subsequent instruction. The subsequent instruction has a data dependency on the flag generating instruction. The flag generating instruction is translated into first and second instructions. The subsequent instruction is translated into at least a third instruction. The first instruction, when executed, generates a result and intermediate flag generation data. The second instruction, when executed, generates a plurality of flags. The first instruction is scheduled to execute before the second and third instructions. The second instruction is scheduled to execute before the third instruction if the third instruction has a data dependency on the second instruction, otherwise the third instruction may be scheduled to execute before the second instruction.

Claims

1. A method, performed by a microprocessor, for executing a flag generating instruction, the method comprising:

(a) translating the flag generating instruction into at least a first instruction and a second instruction;

(b) the first instruction generating intermediate flag generation data upon execution of the first instruction; and

(c) the second instruction, utilizing the intermediate flag generation data, generating a plurality of flags upon execution of the second instruction.

2. The method of claim 1, further comprising scheduling the first instruction for execution before the second instruction.

3. The method of claim 1 wherein the flag generating instruction comprises a CISC instruction and the first and second instructions comprise RISC instructions.

4. The method of claim 1 wherein the flag generating instruction comprises an Intel x86 instruction.

5. The method of claim 1 wherein the flag generating instruction comprises an arithmetic instruction.

6. The method of claim 1 wherein the flag generating instruction comprises a logical instruction.

7. The method of claim 1 wherein the microprocessor comprises a superscalar out-of-order microprocessor.

8. A method, performed by a microprocessor, for scheduling a flag generating instruction and a subsequent instruction, the subsequent instruction having a data dependency on the flag generating instruction, the method comprising:

(a) translating the flag generating instruction into a first instruction and a second instruction, the first instruction, when executed, generating intermediate flag generation data, the second instruction, when executed, utilizing the intermediate flag generation data, generating a plurality of flags;

(b) translating the subsequent instruction into at least a third instruction;

(c) scheduling the first instruction to execute before the second and third instructions; and

(d) scheduling the second instruction to execute before the third instruction if the third instruction has a data dependency on the second instruction.

9. The method of claim 8 wherein the flag generating instruction and the subsequent instruction comprise CISC instructions and the first, second, and third instructions comprise RISC instructions.

10. The method of claim 8 wherein the flag generating instruction comprises an arithmetic instruction.

11. The method of claim 8 wherein the flag generating instruction comprises a logical instruction.

12. The method of claim 8 wherein the flag generating instruction and the subsequent instruction comprise Intel x86 instructions.

13. The method of claim 8 wherein the microprocessor is a superscalar out-of-order microprocessor.

14. A method, performed by a microprocessor, for scheduling a flag generating instruction and a subsequent instruction, the subsequent instruction having a data dependency on the flag generating instruction, the method comprising:

(a) translating the flag generating instruction into a first instruction and a second instruction, the first instruction, when executed, generating intermediate flag generation data, the second instruction, when executed, utilizing the intermediate flag generation data, generating a plurality of flags;

(b) translating the subsequent instruction into at least a third instruction;

(c) scheduling the first instruction to execute before the second and third instructions;

(d) scheduling the second instruction to execute before the third instruction if the third instruction has a data dependency on the second instruction; and

(e) otherwise, scheduling the third instruction to execute before the second instruction.

15. The method of claim 14 wherein the flag generating instruction and the subsequent instruction comprise CISC instructions and the first, second, and third instructions comprise RISC instructions.

16. The method of claim 14 wherein the flag generating instruction comprises an arithmetic instruction.

17. The method of claim 14 wherein the flag generating instruction comprises a logical instruction.

18. The method of claim 14 wherein the flag generating instruction and the subsequent instruction comprise Intel x86 instructions.

19. The method of claim 14 wherein the microprocessor is a superscalar out-of-order microprocessor.