Error generation circuit for testing a digital bus
First Claim
1. A method, comprising the steps of:
- (a) on an integrated circuit of a first device, receiving signals of a bus cycle on a parallel bus, said parallel bus being coupled to said integrated circuit, wherein said signals comprise bus data and a correct parity data, said correct parity data corresponding to said bus data;
(b) on said integrated circuit, simulating receipt of a bus error condition when there is no actual bus error condition on said parallel bus, wherein said step of simulating receipt of a bus error condition comprises the steps of receiving said correct parity data and generating an incorrect parity data based on said correct parity data;
(c) detecting said simulated bus error condition on said integrated circuit in response to said incorrect parity data, and asserting a signal on said parallel bus indicative of said simulated bus error condition; and
(d) setting a bit of a status register in said integrated circuit of said first device to log said simulated bus error condition.
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Accused Products
Abstract
In order to test a parallel digital bus, an integrated circuit adapted for coupling to the bus has a bus error generation circuit which generates and/or simulates bus error conditions on the bus. During test, an error command is loaded into a command register of the bus error generation circuit via the bus. The bus error generation circuit then decodes the command, and either: 1) generates an error condition on the bus during a subsequent bus cycle, or 2) simulates an error condition on the bus during a subsequent bus cycle. A status configuration register in the integrated circuit and status configuration registers in other devices on the bus are then read to determine whether the integrated circuit and other devices properly detected and/or handled the generated or simulated error. By providing a bus error generation circuit in the integrated circuits coupled to a bus inside a personal computer, built-in test of the personal computer is facilitated.
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Citations
7 Claims
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1. A method, comprising the steps of:
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(a) on an integrated circuit of a first device, receiving signals of a bus cycle on a parallel bus, said parallel bus being coupled to said integrated circuit, wherein said signals comprise bus data and a correct parity data, said correct parity data corresponding to said bus data; (b) on said integrated circuit, simulating receipt of a bus error condition when there is no actual bus error condition on said parallel bus, wherein said step of simulating receipt of a bus error condition comprises the steps of receiving said correct parity data and generating an incorrect parity data based on said correct parity data; (c) detecting said simulated bus error condition on said integrated circuit in response to said incorrect parity data, and asserting a signal on said parallel bus indicative of said simulated bus error condition; and (d) setting a bit of a status register in said integrated circuit of said first device to log said simulated bus error condition. - View Dependent Claims (2, 3, 4, 5, 6)
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7. An integrated circuit, comprising:
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a first terminal for coupling to a PAR line of a PCI bus; a second terminal for coupling to a PERR# line of the PCI bus; means for inverting, during execution of a bus error command, a value received on the first terminal; and means for determining a parity value for PCI bus information, and for asserting an error signal onto the second terminal if the parity value differs from a value received from the means for inverting.
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Specification