Methods of forming semiconductor switching devices having trench-gate electrodes

• US 6,051,488 A
• Filed: 01/14/1998
• Issued: 04/18/2000
• Est. Priority Date: 01/14/1997
• Status: Expired due to Term

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Korea Semiconductor Limited (ON Semiconductor Corporation)
• Inventors: Lee, Tea-Sun, Song, Sung-Kyu
• Primary Examiner(s): Limanek, Robert P.
• Assistant Examiner(s): DIETRICH, MICHAEL C
• Application Number:
  US09/007,878
• Time in Patent Office: 825 Days
• Field of Search: 438/259, 438/270, 438/368, 438/547, 438/548, 438/542, 438/589, 438/916, 257/513, 257/608, 257/330, 257/332, 257/212, 257/331
• US Class Current: 438/589
• CPC Class Codes: H01L 21/8234 MIS technology , i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

Methods of forming semiconductor switching devices having trench-gate electrodes include the steps of implanting base region dopants of second conductivity type into a semiconductor substrate to define a preliminary base region therein. A step is then performed to form a trench having sidewalls which extend through the preliminary base region. A sacrificial insulating layer is then formed on the sidewalls of the trench while the implanted base region dopants are simultaneously diffused into the region of first conductivity type. The sacrificial insulating layer is then removed. Next, a gate electrode insulating layer is formed on the sidewalls and on a bottom of the trench. A gate electrode is then formed on the gate electrode insulating layer. Dopants of first conductivity type are then implanted into the semiconductor substrate to define a preliminary source region, which forms a P-N junction with the implanted base region dopants, and into the gate electrode to improve the conductivity thereof. Then a thermal oxide layer is formed on the semiconductor substrate, while the implanted dopants of second and first conductivity type are diffused into the semiconductor substrate. A BPSG layer may also be deposited and reflowed. These latter steps may be utilized to accurately define the depth of the source region and the length of the channel regions extending along the sidewalls of the trenches. Preferred electrical characteristics can therefore be achieved through careful and essentially independent control of the depth/profile of the base region and the depth/profile of the source region.

Claims

1. A method of forming a semiconductor switching device, comprising the steps of:

forming a base region in a semiconductor substrate by implanting base region dopants of second conductivity type into the semiconductor substrate;

forming a trench in the semiconductor substrate;

forming a gate electrode which extends opposite the base region, in the trench;

then

implanting dopants of first conductivity type into the gate electrode and the base region simultaneously; and

forming a thermal oxide layer on the semiconductor substrate, while simultaneously diffusing the implanted dopants of first conductivity type into the base region to define a source region therein.

2. The method of claim 1, wherein the semiconductor substrate contains a drift region of first conductivity type therein extending to a face thereof.

3. The method of claim 2, wherein said gate electrode forming step is preceded by the step of forming a sacrificial oxide layer on sidewalls of the trench while simultaneously diffusing the base region dopants of second conductivity type into the drift region of first conductivity type.

4. The method of claim 2, wherein said trench forming step comprises anisotropically etching the semiconductor substrate to define a preliminary trench and then wet etching sidewalls and a bottom of the preliminary trench.

5. The method of claim 4, wherein said step of anisotropically etching the semiconductor substrate comprises etching the semiconductor substrate using a reactive ion etchant.

6. The method of claim 5, wherein said step of wet etching the sidewalls and bottom of the preliminary trench comprises wet etching the sidewalls and bottom of the preliminary trench using an aqueous solution containing a material selected from the group consisting of fluoric acid, nitric acid and acetic acid.

7. The method of claim 3, wherein said step of forming a sacrificial oxide layer on sidewalls of trench is followed by the step of removing the sacrificial oxide layer using fluoric acid.

8. The method of claim 3, wherein said step of forming a base region by implanting base region dopants comprises implanting dopants of second conductivity type at a first dose level into the face of the semiconductor substrate and implanting dopants of second conductivity type at a second dose level greater than the first dose level.

9. The method of claim 8, wherein said step of forming a gate electrode includes the step of forming a gate electrode insulating layer on sidewalls and a bottom of the trench.

10. A method of forming a semiconductor switching device, comprising the steps of:

forming a first insulating layer on a face of a semiconductor substrate containing a region of first conductivity type therein extending to the face;

implanting dopants of second conductivity type through the first insulating layer and into the region of first conductivity type to define a preliminary base region therein extending to the face;

forming a trench having sidewalls which extend through the preliminary base region and into the region of first conductivity type, at the face of the semiconductor substrate;

forming a sacrificial insulating layer on the sidewalls of the trench while simultaneously diffusing the implanted dopants of second conductivity type into the region of first conductivity type;

removing the sacrificial insulating layer and first insulating layer;

then

forming a gate electrode insulating layer on the sidewalls and a bottom of the trench;

forming a gate electrode on the gate electrode insulating layer;

implanting dopants of first conductivity type into the semiconductor substrate to define a preliminary source region, which forms a P-N junction with the implanted dopants of second conductivity type, while simultaneously implanting dopants of first conductivity type into the gate electrode; and

forming a thermal oxide layer on the semiconductor substrate while simultaneously diffusing the implanted dopants of second and first conductivity type into the semiconductor substrate to define a base region of second conductivity type and a source region of first conductivity type in the base region.

11. The method of claim 10, wherein said step of forming a trench comprises anisotropically etching the semiconductor substrate to define a preliminary trench and then wet etching the preliminary trench.

12. The method of claim 10, wherein said step of forming a trench comprises anisotropically etching the semiconductor substrate using a reactive ion etchant to define a preliminary trench and then wet etching the preliminary trench using an aqueous solution containing a material selected from the group consisting of fluoric acid, nitric acid and acetic acid.

13. The method of claim 12, wherein said removing step comprises etching the sacrificial insulating layer using fluoric acid.

14. The method of claim 11, further comprising the step of forming a layer of borophosphosilicate glass on the thermal oxide layer and then reflowing the layer of borophosphosilicate glass.

15. The method of claim 12, wherein said step of implanting dopants of second conductivity type includes the steps of performing a blanket implant of second conductivity type dopants at a first dose level through the first insulating layer and then performing a selective implant of second conductivity type dopants at a second dose level, greater than the first dose level, through the first insulating layer.

16. The method of claim 12, wherein said wet etching step comprises etching about 1000 Å

from a sidewall of the preliminary trench.