Oscillator with clock output inhibition control

• US 6,052,035 A
• Filed: 12/04/1998
• Issued: 04/18/2000
• Est. Priority Date: 03/19/1998
• Status: Expired due to Term

• Current Assignee: Microchip Technology Incorporated
• Original Assignee: Microchip Technology Incorporated
• Inventors: Pyska, Michael S., Ellison, Ryan Scott, Nolan, James B.
• Primary Examiner(s): Grimm, Siegfried H.
• Application Number:
  US09/205,758
• Time in Patent Office: 501 Days
• Field of Search: 331/111, 331/143, 331/176, 331/179, 331/74, 331/75
• US Class Current: 331/74
• CPC Class Codes: H03K 3/011 Modifications of generator to compensate for variations in physical values, e.g. voltage, temperature to maintain energy constant H03K3/015
• CPC Class Codes: H03K 3/0231 Astable circuits H03K3/0315 takes precedence

Abstract

An oscillator with temperature compensation produces a stable clock frequency over wide variations of ambient temperature, and it includes an oscillation generator, two independent current generators, a transition detector and a clock inhibitor. The outputs of the two programmable, independent current generators are combined to provide a capacitor charging current that is independent of temperature. The oscillator is capable of three modes of operation: fast mode, slow/low power mode and sleep mode, which are controlled by the transition detector in response to external control signals. When the transition detector transitions from one mode to another, it controls the clock inhibitor to block a clock output of the oscillator generator for a predetermined number of clock cycles to allow the clock output to stabilize. The oscillator is implemented on a single, monolithic integrated circuit.

Claims

1. An oscillator, comprising:

a clock generator having an output, said clock generator generating a clock signal at said generator output;

an inhibitor having a control input, a clock output, and a clock input coupled to said generator output, said inhibitor inhibiting the transmission of signals from said clock input to said clock output when receiving an activation signal at said control input; and

a detector having an input and an output coupled to said inhibitor control input, said detector detecting an oscillator control signal at said detector input, thereby generating said activation signal at said detector output;

wherein the clock generator comprises at least a timing capacitor and at least a first current generator for periodically charging said timing capacitor, said first current generator being constructed and arranged to selectively generate at least two different currents;

wherein said clock generator is constructed and arranged to selectively generate a clock signal of at least two different clock frequencies;

wherein the circuit has at least a first operating mode and a second operating mode, the clock frequency of the clock signal of the second operating mode being lower than the clock frequency of the clock signal of the first operating mode; and

wherein the first operating mode is determined by the selection of a resistor which is internal to the first current generator.

2. The circuit in accordance with claim 1 wherein the first operating mode is further determined by programming a plurality of calibration switches which are internal to the first current generator.

3. An oscillator, comprising:

a clock generator having an output, said clock generator generating a clock signal at said generator output;

an inhibitor having a control input, a clock output, and a clock input coupled to said generator output, said inhibitor inhibiting the transmission of signals from said clock input to said clock output when receiving an activation signal at said control input; and

a detector having an input and an output coupled to said inhibitor control input, said detector detecting an oscillator control signal at said detector input, thereby generating said activation signal at said detector output;

wherein the clock generator comprises at least a timing capacitor and at least a first current generator for periodically charging said timing capacitor, said first current generator being constructed and arranged to selectively generate at least two different currents;

wherein said clock generator is constructed and arranged to selectively generate a clock signal of at least two different clock frequencies;

wherein the circuit has at least a first operating mode and a second operating mode, the clock frequency of the clock signal of the second operating mode being lower than the clock frequency of the clock signal of the first operating mode; and

wherein the second operating mode is determined by the selection of a second resistor which is internal to the first current generator.

4. The circuit in accordance with claim 3 wherein the second operating mode is further determined by programming a plurality of calibration switches which are internal to the first current generator.

5. An oscillator, comprising:

a clock generator having an output, said clock generator generating a clock signal at said generator output;

an inhibitor having a control input, a clock output, and a clock input coupled to said generator output, said inhibitor inhibiting the transmission of signals from said clock input to said clock output when receiving an activation signal at said control input; and

a detector having an input and an output coupled to said inhibitor control input, said detector detecting an oscillator control signal at said detector input, thereby generating said activation signal at said detector output; and

wherein said inhibitor comprises a counter.

6. The circuit in accordance with claim 5 wherein said counter starts counting clock pulses of said clock signal upon receiving said activation signal at said control input.

7. The circuit in accordance with claim 6 wherein said inhibitor inhibits the transmission of signals from said clock input to said clock output until said counter has counted a predetermined number of clock pulses.

8. The circuit in accordance with claim 7 wherein said inhibitor permits the transmission of signals from said clock input to said clock output after said counter has counted said predetermined number of clock pulses.

9. The circuit in accordance with claim 7 wherein said predetermined number of clock pulses is programmable.