Nonvolatile configuration cells and cell arrays

• US 6,052,309 A
• Filed: 08/30/1999
• Issued: 04/18/2000
• Est. Priority Date: 03/14/1996
• Status: Expired due to Fees

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Madurawe, Raminda U., Sansbury, James D.
• Primary Examiner(s): ZARABIAN, AMIR
• Application Number:
  US09/386,042
• Time in Patent Office: 232 Days
• Field of Search: 365/185.28, 365/185.18, 365/185.1, 365/185.24
• US Class Current: 365/185.28
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 16/0441 comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
• CPC Class Codes: G11C 5/00 Details of stores covered by group G11C11/00
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: H03K 19/17748 Structural details of configuration resources
• CPC Class Codes: H03K 19/1776 for memories
• CPC Class Codes: H03K 19/17772 for powering on or off
• CPC Class Codes: H03K 19/1778 Structural details for adapting physical parameters
• CPC Class Codes: H03K 19/17784 for supply voltage

Abstract

A memory cell (400) used to store data in an integrated circuit. The memory cell (400) is static, nonvolatile, and programmable. The layout of the memory cell is compact. A logic high output from the memory cell (400) is about VDD and a logic low output is about VSS. The memory cell (400) of the present invention includes a programmable memory element (515). In one embodiment, the programmable memory element (515) is coupled between supply voltage (510) and an output node (405). A pull-down device (525) is coupled between another supply voltage (505) and the output node (405). The memory cell (400) may be used to store the configuration information for a programmable logic device (121).

Claims

1. A method of configuring a programmable memory element comprising:

placing a VEE voltage at a tunnel dielectric source, wherein the tunnel dielectric source is coupled through a tunnel dielectric to a shared floating gate of a programmable memory program cell and a programmable memory read cell;

placing a voltage of about VSS or less on a control gate of the programmable memory program cell;

placing a voltage of about VSS or less on a control gate of the programmable memory read cell;

grounding a drain of the programmable memory read cell;

passing about VSS through a pull-down device to a source of the programmable memory read cell; and

transferring electrons from the shared floating gate of the programmable memory read cell through the tunnel dielectric to the tunnel dielectric source, thereby adjusting a threshold voltage of the programmable memory read cell so that a reasonable voltage on the control gate of the programmable memory read cell will turn on the programmable memory read cell.

2. The method of claim 1 wherein in the VEE voltage is a voltage in a range from about 11 volts to about 15 volts.

3. The method of claim 1 wherein the reasonable voltage is a voltage in a range from about VSS to about VDD.

4. The method of claim 1 wherein the reasonable voltage is generated by a charge pump or bias voltage generator.

5. The method of claim 1 wherein the pull-up resistor is formed using a thin film transistor.

6. The method of claim 1 wherein the pull-up resistor comprises a transistor.