Method for tightening erase threshold voltage distribution in flash electrically erasable programmable read-only memory (EEPROM)
First Claim
1. A method for erasing a flash Electrically-Erasable Programmable Read-Only Memory (EEPROM) which includes a plurality of field effect transistor memory cells each having a source, drain, floating gate and control gate, comprising the steps of:
- (a) connecting a power supply to the sources of the cells;
(b) determining a state of erasure of the cells; and
(c) applying an erase pulse to the cells with the power supply configured in accordance with a predetermined function of the state of erasure.
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Abstract
A flash Electrically-Erasable Programmable Read-Only Memory includes a plurality of field effect transistor memory cells each having a source, drain, floating gate and control gate. The state of erasure of the cells is determined by sensing the source voltage of the cells. An erase pulse is applied to the cells by a power supply which applies a source pull-up voltage to the cells configured in accordance with a predetermined function of the state of erasure. The power supply includes a variable current source and/or a resistor which are continuously adjusted as the erase operation progresses to provide an optimal vertical field across the tunnel oxide layers of the cells. Alternatively, the power supply can include a voltage regulator which is continuously adjusted to directly apply an optimal source voltage to the cells. The state of erasure can also be predetermined as a function of time or applied erase pulses, and the power supply adjusted in an open loop manner. The state of erasure of the memory is preferably monitored by applying alternating erase and monitoring pulses to the cells. The source voltage is sensed during the monitoring pulses to provide an accurate indication of the erase state. The source current drive during the monitoring pulses is sufficiently reduced from the current drive during the erase pulses that the source voltage will not clamp to the main source supply voltage, thereby providing a correlation between the source voltage and erase state.
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Citations
30 Claims
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1. A method for erasing a flash Electrically-Erasable Programmable Read-Only Memory (EEPROM) which includes a plurality of field effect transistor memory cells each having a source, drain, floating gate and control gate, comprising the steps of:
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(a) connecting a power supply to the sources of the cells; (b) determining a state of erasure of the cells; and (c) applying an erase pulse to the cells with the power supply configured in accordance with a predetermined function of the state of erasure. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A flash Electrically-Erasable Programmable Read-Only Memory (EEPROM) which includes a plurality of field effect transistor memory cells each having a source, drain, floating gate and control gate, comprising:
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a power supply; and a controller which cooperates with the power supply to perform the steps of; (a) determining a state of erasure of the cells; and (b) applying an erase pulse to the cells with the power supply configured in accordance with a predetermined function of the state of erasure. - View Dependent Claims (17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30)
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Specification