Method for tightening erase threshold voltage distribution in flash electrically erasable programmable read-only memory (EEPROM)

• US 6,052,310 A
• Filed: 08/12/1998
• Issued: 04/18/2000
• Est. Priority Date: 08/12/1998
• Status: Expired due to Term

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Advanced Micro Devices SDN Berhad (Advanced Micro Devices, Inc.)
• Inventors: Sunkavalli, Ravi S.
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Nguyen, Tuan T.
• Application Number:
  US09/132,981
• Time in Patent Office: 615 Days
• Field of Search: 365/185.29, 365/185.3, 365/185.33, 365/185.21, 365/226
• US Class Current: 365/185.29
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 16/3445 Circuits or methods to verify correct erasure of nonvolatile memory cells

Abstract

A flash Electrically-Erasable Programmable Read-Only Memory includes a plurality of field effect transistor memory cells each having a source, drain, floating gate and control gate. The state of erasure of the cells is determined by sensing the source voltage of the cells. An erase pulse is applied to the cells by a power supply which applies a source pull-up voltage to the cells configured in accordance with a predetermined function of the state of erasure. The power supply includes a variable current source and/or a resistor which are continuously adjusted as the erase operation progresses to provide an optimal vertical field across the tunnel oxide layers of the cells. Alternatively, the power supply can include a voltage regulator which is continuously adjusted to directly apply an optimal source voltage to the cells. The state of erasure can also be predetermined as a function of time or applied erase pulses, and the power supply adjusted in an open loop manner. The state of erasure of the memory is preferably monitored by applying alternating erase and monitoring pulses to the cells. The source voltage is sensed during the monitoring pulses to provide an accurate indication of the erase state. The source current drive during the monitoring pulses is sufficiently reduced from the current drive during the erase pulses that the source voltage will not clamp to the main source supply voltage, thereby providing a correlation between the source voltage and erase state.

Claims

1. A method for erasing a flash Electrically-Erasable Programmable Read-Only Memory (EEPROM) which includes a plurality of field effect transistor memory cells each having a source, drain, floating gate and control gate, comprising the steps of:

(a) connecting a power supply to the sources of the cells;

(b) determining a state of erasure of the cells; and

(c) applying an erase pulse to the cells with the power supply configured in accordance with a predetermined function of the state of erasure.

2. A method as in claim 1, in which:

step (b) comprises sensing a source voltage of the cells; and

step (c) comprises configuring the power supply as a predetermined function of the sensed source voltage.

3. A method as in claim 1, in which step (c) comprises configuring the power supply as a predetermined function of erase time.

4. A method as in claim 1, in which step (c) comprises configuring the power supply as a predetermined function of a number of erase pulses applied to the cells.

5. A method as in claim 1, in which:

the power supply comprises a current source; and

step (c) comprises configuring the current source to limit current flowing therefrom to the cells to a value according to said predetermined function of the state of erasure.

6. A method as in claim 5, in which:

the current source comprises a continuously variable current limiting element; and

step (c) comprises controlling the element in accordance with said predetermined function of the state of erasure.

7. A method as in claim 5, in which:

the current source comprises a plurality of current limiting elements which limit current flowing therefrom to the cells to different values respectively; and

step (c) comprises connecting one of the current limiting elements to the sources of the cells which is selected in accordance with said predetermined function of the state of erasure.

8. A method as in claim 1, in which:

the power supply comprises a constant current source;

step (c) comprises configuring the current source to supply a value of current to the cells according to said predetermined function of the state of erasure.

9. A method as in claim 8, in which:

the constant current source comprises a continuously variable current sourcing element; and

step (c) comprises controlling the element in accordance with said predetermined function of the state of erasure.

10. A method as in claim 8, in which:

the current source comprises a plurality of current sourcing elements which supply different values of current to the cells respectively; and

step (c) comprises connecting one of the current sourcing elements to the sources of the cells which is selected in accordance with said predetermined function of the state of erasure.

11. A method as in claim 1, in which:

the power supply comprises a resistance;

step (c) comprises configuring the resistance to have a value according to said predetermined function of the state of erasure.

12. A method as in claim 11, in which:

the resistance comprises a continuously variable resistance element; and

step (c) comprises controlling the element to provide a resistance in accordance with said predetermined function of the state of erasure.

13. A method as in claim 11, in which:

the resistance comprises a plurality of resistance elements which provide different values of resistance respectively; and

step (c) comprises connecting one of the elements to the sources of the cells which is selected in accordance with said predetermined function of the state of erasure.

14. A method as in claim 1, in which:

the power supply comprises a voltage source; and

step (c) comprises configuring the voltage source to apply a source voltage to the cells having a value according to said predetermined function of the state of erasure.

15. A method as in claim 14, in which the voltage source comprises a continuously variable voltage regulator;

and

step (c) comprises controlling the regulator to provide a resistance in accordance with said predetermined function of the state of erasure.

16. A flash Electrically-Erasable Programmable Read-Only Memory (EEPROM) which includes a plurality of field effect transistor memory cells each having a source, drain, floating gate and control gate, comprising:

a power supply; and

a controller which cooperates with the power supply to perform the steps of;

(a) determining a state of erasure of the cells; and

(b) applying an erase pulse to the cells with the power supply configured in accordance with a predetermined function of the state of erasure.

17. A memory as in claim 16, further comprising a sensor for sensing a source voltage of the cells, in which:

step (a) comprises controlling the sensor to sense the source voltage; and

step (b) comprises configuring the power supply as a predetermined function of the source voltage.

18. A memory as in claim 16, in which step (b) comprises configuring the power supply as a predetermined function of erase time.

19. A memory as in claim 16, in which step (b) comprises configuring the power supply as a predetermined function of a number of erase pulses applied to the cells.

20. A memory as in claim 16, in which:

the power supply comprises a current source; and

step (b) comprises configuring the current source to limit current flowing therefrom to the cells to a value according to said predetermined function of the state of erasure.

21. A memory as in claim 20, in which:

the current source comprises a continuously variable current limiting element; and

step (b) comprises controlling the element in accordance with said predetermined function of the state of erasure.

22. A memory as in claim 20, in which:

the current source comprises a plurality of current limiting elements which limit current flowing therefrom to the cells to different values respectively; and

step (b) comprises connecting one of the current limiting elements to the sources of the cells which is selected in accordance with said predetermined function of the state of erasure.

23. A memory as in claim 16, in which:

the power supply comprises a constant current source;

step (b) comprises configuring the current source to supply a value of current to the cells according to said predetermined function of the state of erasure.

24. A memory as in claim 23, in which:

the constant current source comprises a continuously variable current sourcing element; and

step (b) comprises controlling the element in accordance with said predetermined function of the state of erasure.

25. A memory as in claim 23, in which:

the current source comprises a plurality of current sourcing elements which supply different values of current to the cells respectively; and

step (b) comprises connecting one of the current sourcing elements to the sources of the cells which is selected in accordance with said predetermined function of the state of erasure.

26. A memory as in claim 16, in which:

the power supply comprises a resistance;

step (b) comprises configuring the resistance to have a value according to said predetermined function of the state of erasure.

27. A memory as in claim 26, in which:

the resistance comprises a continuously variable resistance element; and

step (b) comprises controlling the element to provide a resistance in accordance with said predetermined function of the state of erasure.

28. A memory as in claim 26, in which:

the resistance comprises a plurality of resistance elements which provide different values of resistance respectively; and

step (b) comprises connecting one of the elements to the sources of the cells which is selected in accordance with said predetermined function of the state of erasure.

29. A memory as in claim 16, in which:

the power supply comprises a voltage source; and

step (c) comprises configuring the voltage source to apply a source voltage to the cells having a value according to said predetermined function of the state of erasure.

30. A memory as in claim 29, in which the voltage source comprises a continuously variable voltage regulator;

and

step (c) comprises controlling the regulator to provide a resistance in accordance with said predetermined function of the state of erasure.