High speed internetworking traffic scaler and shaper
First Claim
1. A traffic scaling and shaping apparatus for shaping the output traffic in a high speed computer network device, said apparatus comprising:
- a timing mechanism for the scheduling of a plurality of logical queues, each logical queue having associated therewith valid data queues of at least one priority type;
a parameter table for storing for each logical queue a plurality of parameter values used to control the shaping of output traffic;
a traffic scaler mechanism for manipulating the traffic shaper parameter values for each of said logical queues;
a traffic queue allocation manager for allocating each said valid data queue for each said logical queue to a different one of output ports;
a plurality of queue priority arbiters associated with each output port for performing internal arbitration of each valid data queue allocated to it, said internal arbitration resulting in a plurality of priority-based queues for said each output port;
a plurality of port priority arbiters, each port priority arbiter corresponding to a separate priority type, for selecting a valid queue for each priority type; and
a bus DMA arbiter for selecting a final queue to be processed from said selected valid queues of each priority type.
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Accused Products
Abstract
A method and system are provided for traffic shaping and bandwidth scaling in a high speed internetworking device. A slot time wheel mechanism is provided for traffic rate control and a credit/debit mechanism is provided for traffic shaping and scaling. The high speed traffic scaler and shaper incorporates a programmable slot time wheel, a traffic scaler state machine, a traffic shaper parameter table and a traffic scaler processor. The traffic scaler processor incorporates a traffic queue allocation manager, a queue priority arbiter, a port enable selector, a port priority arbiter and a DMA channel arbiter. The traffic queue allocation manager and the queue priority, port priority and DMA channel arbiters are each controlled by a corresponding state machine. The parameters in the traffic shaper parameter table are dynamically updated for each logical queue and are used to enable the credit/debit mechanism.
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Citations
26 Claims
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1. A traffic scaling and shaping apparatus for shaping the output traffic in a high speed computer network device, said apparatus comprising:
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a timing mechanism for the scheduling of a plurality of logical queues, each logical queue having associated therewith valid data queues of at least one priority type; a parameter table for storing for each logical queue a plurality of parameter values used to control the shaping of output traffic; a traffic scaler mechanism for manipulating the traffic shaper parameter values for each of said logical queues; a traffic queue allocation manager for allocating each said valid data queue for each said logical queue to a different one of output ports; a plurality of queue priority arbiters associated with each output port for performing internal arbitration of each valid data queue allocated to it, said internal arbitration resulting in a plurality of priority-based queues for said each output port; a plurality of port priority arbiters, each port priority arbiter corresponding to a separate priority type, for selecting a valid queue for each priority type; and a bus DMA arbiter for selecting a final queue to be processed from said selected valid queues of each priority type. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. For use in a high speed computer network device, a method for scaling and shaping the output traffic, said method comprising:
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scheduling a plurality of logical queues sequentially, each logical queue having associated therewith valid data queues of at least one priority type; storing for each logical queue, a plurality of parameter values that are used to control the shaping of output traffic; manipulating the parameter values corresponding to each of said logical queues dynamically; allocating to each said valid data queue, corresponding to each said logical queue, a different one of output ports; performing queue priority arbitration for each valid data queue allocated to each output port to generate a plurality of priority-based queues for said each output port; performing port priority arbitration for each valid data queue at said each output port according to said priority type to generate a selected valid queue for each priority type; and performing bus DMA arbitration to select a final queue from said selected valid queues of each priority type. - View Dependent Claims (15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26)
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Specification