Frequency hopping synchronization and tracking in a digital communication system

• US 6,052,406 A
• Filed: 05/02/1997
• Issued: 04/18/2000
• Est. Priority Date: 05/02/1997
• Status: Expired due to Term

• Current Assignee: Harris Corporation (L3Harris Technologies, Inc.)
• Original Assignee: ITT Manufacturing Enterprises, Inc. (ITT, Inc.)
• Inventors: Epstein, Marvin A., Blois, Gary V., Fine, Joseph M.
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): DEPPE, BETSY LEE
• Application Number:
  US08/850,231
• Time in Patent Office: 1,082 Days
• Field of Search: 375/202, 375/200, 375/355, 375/208, 375/209, 375/210, 375/367, 375/365, 375/362, 375/354, 375/371
• US Class Current: 375/134
• CPC Class Codes: H04B 1/7156 Arrangements for sequence synchronisation
• CPC Class Codes: H04B 2001/71563 Acquisition
• CPC Class Codes: H04B 2001/71566 Tracking
• CPC Class Codes: H04J 13/00 Code division multiplex systems for frequency hopping H04B1/713
• CPC Class Codes: H04L 7/10 Arrangements for initial synchronisation

Abstract

There is disclosed an improved frequency hopping synchronization and tracking system for bit syncing and frame syncing a digital data signal as transmitted by a radio transmitter. A detection means responsive to incoming data samples representative of the phasing signal portion of the digital data signal partitions the data samples into alternating first and second sample sequences and correlates the samples against a frequency hop modulation code reference sequence to provide an initial data signal detection. A post-detection means responsive to the initial detection and to the frequency hop modulation code reference sequence correlates the incoming data samples and compares the spectral power of the correlated data samples to a threshold value to provide bit sync of the detected data signal. Tracking means responsive to the bit sync and to the input samples captures a frame signal and generates histograms of data bit transitions for producing an error signal indicative of the difference of the transmitted clock rate and the sampling position of the received bit. A clock means responsive to the error signal produced by the histogram process can be adjusted according to the error signal to enable sampling of each received data bit to occur relatively at the center of each bit to ensure reliable decoding or detection of a digital data signal in a noisy channel at the receiver.

Claims

1. A digital communications system, comprising:

a transmitter for transmitting a digital data signal via a noisy transmission path, said digital data signal having a phasing signal portion and a framing signal portion; and

a receiver responsive to said transmitted signal, said receiver comprising;

a detector responsive to incoming data samples representative of said phasing signal portion of said digital data signal, said detector partitioning said incoming data samples into alternating first and second sample sequences and correlating said sequences against a hop frequency modulation code reference sequence to provide an output signal indicative of correlated data samples and of a data signal detection;

a post-detector responsive to said output signal and to said hop frequency modulation code reference sequence for correlating said incoming data samples and comparing a spectral power of said correlated data samples to a threshold value to provide a sync output signal indicative of frequency hop synchronization of said digital data signal;

a tracker responsive to said sync output signal and said digital data signal for periodically providing histograms of data bit transitions for producing an error signal indicative of the difference of the transmitted clock rate and the sampling position of a received bit; and

a clock responsive to said error signal to provide a clock signal according to said error signal to drive sampling of received data bits toward the center of each bit.

2. The digital communications system according to claim 1, wherein said detector further includes a comparator adapted to compare the spectral power of said correlated data samples with a threshold energy at particular sample points to determine the presence of said digital data signal.

3. The digital communications system according to claim 1, wherein said incoming data samples are provided to said detector at a rate of 80 KS/sec, and wherein every other sample of said incoming data samples is selected for partitioning into said alternating first and second sample sequences.

4. The digital communications system according to claim 1, wherein said post-detector further includes means for jam synchronizing, to a predetermined sampling frequency, said incoming data samples corresponding to correlated data samples whose spectral power exceeds said threshold value.

5. The digital communications system according to claim 1, wherein said post-detector further includes means for decoding said hop frequency modulation code reference sequence to determine a hop-time offset clock drift.

6. The digital communications system according to claim 5, further including extrapolation means responsive to said hop-time offset clock drift for adjusting said clock signal to remove phase error accumulations resulting from an interval between termination of said post-detector and initiation of said tracker.

7. The digital communications system according to claim 1, wherein said post-detector includes Bessel shaping filters for correlating said incoming data samples.

8. The digital communications system according to claim 1, further including means responsive to said histograms for detecting fading of said digital data signal.

9. The digital communications system according to claim 1, further including:

means for portioning a data bit period into a plurality of bins for storing a weight factor in each bin indicative of the distance of the data bit center of the data bit edge.

10. A method of detecting a phasing signal pattern and a framing signal in a transmitted digital data signal for using said transmitted digital data signal to synchronize a clock at a receiver, the method comprising the steps of:

receiving incoming data samples representative of said digital data signal at a predetermined sampling rate R;

sampling every other said received incoming data samples and alternately partitioning said every other said sampled incoming data sample into a first odd and second even sample sequences, whereby said first odd and second even sample sequences sampling rates are one-fourth of said predetermined sampling rate R;

correlating said odd and even sample sequences against a hop frequency modulation reference code sequence to obtain odd and even correlation values;

summing the magnitudes of said odd and even correlation values;

computing a power measurement during a predetermined period representative of the spectral energy of said odd and even correlated values;

comparing said power measurement with a stored signal energy estimate to provide an output signal if the comparison exceeds a given threshold value, wherein said output signal includes an indication of the start and end points of correlated samples;

merging said odd and even sample sequences into a unified sample sequence;

generating first odd and second even reference sample sequences from a combination of preamble bit pattern samples of a known preamble bit pattern and the hop frequency modulation reference code sequence;

correlating said odd and even reference sample sequences against said unified sample sequence to provide multiple hop-width correlation samples having multiple hop-width correlation values;

computing a post-detection power measurement during a predetermined period representative of the spectral energy of said hop-width correlation values;

comparing said post-detection power measurement with a second stored signal energy estimate to provide a sync output signal if the comparison exceeds a given post-detection threshold value;

decoding said hop frequency modulation reference code sequence to determine a hop-time offset clock drift; and

adjusting the receiver clock to remove phase error resulting from said hop-time offset clock drift.

11. The method of claim 10, further including the steps of:

repositioning said multiple hop-width correlation samples by jam synchronizing said hop-width correlation samples to a predetermined sampling frequency; and

deleting clock offset pulses associated with said repositioning to remove residual phase error;

wherein said steps are performed prior to said decoding step.

12. The method of claim 11, wherein said predetermined sampling rate R and said predetermined sampling frequency are 80 KHz, and wherein said unified sample sequence, said first odd and second even reference sample sequence, and said multiple correlation sample sequence rates are 40 KHz.

13. The method of claim 10, wherein said multiple hop-width correlation samples include even and odd hop-width correlations, said even hop-width correlations determined by summing the absolute values of even modulation code segment correlations and even preamble segment correlations, said odd hop-width correlations determined by summing the absolute values of odd modulation code segment correlations and odd preamble segment correlations.

14. The method of claim 10, further including tracking the incoming data samples by:

periodically generating histograms of data transition positions for each frequency hop;

updating said generated histograms at the tracking rate to produce a phase metric error;

applying said phase metric error to a clock for synchronizing said clock to said transmitted data signal.

15. The method of claim 14, wherein the step of generating said histograms comprises the steps of:

collecting data samples for each frequency hop during a given frame period;

detecting transition between said data samples;

linearly interpolating said data samples upon detection of a transition to provide a fractional sample position;

calculating a bin number for each transition;

incrementing an associated bin counter to form histograms for said data samples.

16. The method of claim 15, further including the steps of:

applying a weighting curve to said histograms to provide said phase error metric;

comparing the ratio of the difference of bin counts near bit edge and bin counts near bin center to the total count for a particular bin to provide threshold signals determinative of input signal fading.

17. The method of claim 16, wherein said particular bin is bin 6.

18. The method of claim 15, wherein said data samples used for said histogram generation comprise all frequency hop active samples per hop, and wherein said all frequency hop active samples per hop are a subset of all frequency hop total samples per hop.

19. The method of claim 15, wherein the steps of generating histograms includes partitioning of the data bit period into a predetermined number of bins according to the system sampling rate.

20. The method of claim 19, wherein said data bit period is partitioned into 16 bins with 4 bins between samples.

21. The method of claim 10, wherein said post-detection power measurement comparison includes the steps of:

determining a mark representative of the maximum of said hop-width correlation values;

comparing said mark with said post-detection threshold value.

22. The method of claim 21, wherein said determination includes applying parabolic fitting on three adjacent hop-width correlation values to determine the maximum value at the optimum sampling point.

23. In a receiver of a digital communication system, a method of achieving synchronization with a digital signal received by the receiver and modulated in accordance with a modulation code known to the receiver, in order to allow the receiver to time align the sampling of the digital signal to a timing of the digital signal, the digital signal having a synchronization portion and a data portion, the method comprising the steps of:

(a) accumulating at the receiver a sequence of samples of the synchronization portion of the digital signal;

(b) detecting and coarsely estimating the timing of the digital signal by correlating samples in the sequence of samples with a modulation reference code sequence;

(c) finely estimating the timing of the digital signal by correlating samples of the sequence of samples with a refined reference sequence at a plurality of different correlation timings offset by predetermined durations from the coarsely estimated timing of the digital signal, a finely estimated timing of the digital signal being determined from correlations at the plurality of different correlation timings; and

(d) adjusting a timing of a clock of the receiver in accordance with the finely estimated timing of the digital signal to synchronize sampling of the digital signal at the receiver to the timing of the digital signal.

24. The method of claim 23, wherein step (b) includes identifying the coarsely estimated timing of the digital signal as a time when a correlation value determined from values of the samples correlated with the modulation reference code sequence exceeds a threshold.

25. The method of claim 23, wherein step (b) includes selecting every other sample in the sequence of samples to form a sub-sequence, and forming odd and even sample sequences from alternating samples of the sub-sequence, the odd and even sample sequences being correlated with the modulation reference code sequence to detect the digital signal and to determine the coarsely estimated timing of the digital signal.

26. The method of claim 23, wherein step (c) includes:

(c1) computing a sum of the correlated samples at each of the plurality of different correlation timings;

(c2) determining a finely estimated timing of the digital signal from the computed sums; and

(c3) identifying the finely estimated timing of the digital signal as the correlation timing associated with the largest of the computed sums.

27. The method of claim 23, wherein step (c) includes:

(c1) computing a sum of the correlated samples at each of the plurality of different correlation timings;

(c2) determining a finely estimated timing of the digital signal from the computed sums; and

(c3) fitting a parabolic curve to the sums of the correlated samples at the plurality of different correlation timings and identifying the finely estimated timing of the digital signal as a maximum point on the parabolic curve.

28. The method of claim 23, wherein step (c) includes:

(c1) forming an odd reference sequence and an even reference sequence from the sequence of samples accumulated in step (a);

(c2) selecting every other sample in the sequence of samples accumulated in step (a) to form a refined sample sequence;

(c3) correlating the odd reference sequence with the refined sample sequence at a set of said plurality of different correlation timings; and

(c4) correlating the even reference sequence with the refined sample sequence at a set said plurality different correlation timings.

29. The method of claim 23, wherein the refined reference sequence is a Bessel reference sample sequence.

30. The method of claim 23, wherein the plurality of different correlation timings are offset by i sample periods from the coarsely estimated timing of the digital signal, where i is a positive integer, a negative integer or zero.

31. The method of claim 23, wherein the digital signal is a frequency hopped signal.

32. The method of claim 23, further comprising the steps of:

(e) sampling bits of the data portion of the digital signal to acquire a sequence of digital sample values;

(f) determining data bit transition times of the digital signal from the digital sample values;

(g) forming a histogram of data bit transition times;

(h) calculating a phase error metric as a function of the histogram; and

(i) using the phase error metric to adjust a timing reference of the receiver to synchronize the sampling with data bits of the digital signal.

33. A digital communication system, comprising:

a transmitter adapted to transmit a digital signal modulated in accordance with a modulation code and having a synchronization portion and a data portion;

a receiver adapted to detect the digital signal and synchronize sampling of the digital signal with a bit timing of the digital signal, said receiver comprising;

an analog-to-digital (A/D) converter that samples the digital signal to produce a sequence of samples of the synchronization portion of the digital signal;

a pre-detector adapted to detect and coarsely estimate a timing of the digital signal by correlating samples in the sequence of samples with a modulation reference code sequence;

a post-detector that finely estimates the timing of the digital signal by correlating samples of the sequence of samples with a refined reference sequence at a plurality of different correlation timings offset by predetermined durations from the coarsely estimated timing of the digital signal, said post-detector determining a finely estimated timing of the digital signal from correlations at the plurality of different correlation timings; and

an adjustable clock that provides a timing reference for sampling the digital signal, the timing of said adjustable clock being adjusted in accordance with the finely estimated timing of the digital signal to synchronize sampling of the digital signal at said receiver to the timing of the digital signal.

34. The system of claim 33, wherein said pre-detector identifies the coarsely estimated timing of the digital signal as a time when a correlation value determined from values of the samples correlated with the modulation reference code sequence exceeds a threshold.

35. The system of claim 33, wherein said pre-detector selects every other sample in the sequence of samples to form a sub-sequence and forms odd and even sample sequences from alternating samples of the sub-sequence, said pre-detector correlating the odd and even sample sequences with the modulation reference code sequence to detect the digital signal and to determine the coarsely estimated timing of the digital signal.

36. The system of claim 33, wherein said post-detector computes a sum of the correlated samples at each of the plurality of different correlation timings and determines a finely estimated timing of the digital signal from the computed sums, said post-detector identifying the finely estimated timing of the digital signal as the correlation timing associated with the largest of the computed sums.

37. The system of claim 33, wherein said post-detector computes a sum of the correlated samples at each of the plurality of different correlation timings and determines a finely estimated timing of the digital signal from the computed sums, said post-detector fitting a parabolic curve to the sums of the correlated samples at the plurality of different correlation timings and identifying the finely estimated timing of the digital signal as a maximum point on the parabolic curve.

38. The system of claim 33, wherein said post-detector forms an odd reference sequence and an even reference sequence from the sequence of samples and selects every other sample in the sequence of samples to form a refined sample sequence, said post-detector correlating the odd reference sequence with the refined sample sequence at a plurality of different correlation timings and correlating the even reference sequence with the refined sample sequence at a plurality of different correlation timings.

39. The system of claim 33, wherein the refined reference sequence is a Bessel reference sample sequence.

40. The system of claim 33, wherein the plurality of different correlation timings are offset by i sample periods from the coarsely estimated timing of the digital signal, where i is a positive integer, a negative integer or zero.

41. The system of claim 33, wherein the digital signal is a frequency hopped signal.

42. The system of claim 33, wherein said A/D converter samples bits of the data portion of the digital signal to acquire a sequence of digital sample values, the system further comprising a processor receiving the sequence of digital sample values and determining data bit transition times of the digital signal from the digital sample values, said processor forming a histogram of data bit transition times and calculating a phase error metric as a function of the histogram, said adjustable clock being responsive to the phase error metric to adjust the timing reference of the receiver to synchronize the timing of the samples with data bits of the digital signal.