Multi-threaded bus master

• US 6,052,513 A
• Filed: 06/05/1996
• Issued: 04/18/2000
• Est. Priority Date: 06/05/1996
• Status: Expired due to Term

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Compaq Computer Corporation (HP Inc.)
• Inventors: MacLaren, John M.
• Primary Examiner(s): Sheikh, Ayaz R.
• Assistant Examiner(s): PANCHOLI, JIGAR K
• Application Number:
  US08/659,355
• Time in Patent Office: 1,413 Days
• Field of Search: 395/280-298, 395/306-309, 395/728, 395/729, 395/731, 395/732
• US Class Current: 710/114
• CPC Class Codes: G06F 13/364 using independent requests or grants, e.g. using separated request and grant lines

Abstract

Access to bus devices on a bus is granted in a computer system, with each bus device asserting a request signal to request the bus. A detector determines if a bus device is multi-threaded or single-threaded. An arbiter masks or does not mask the request signal of a retried bus device based on whether the bus device is a multi-threaded device. The arbiter masks the request signal of a retried bus device if it is a single-threaded device, but does not mask the request signal if the retried bus device is a multi-threaded device. The bus device request includes a delayed request transaction, and the bus includes a PCI bus.

Claims

1. A computer system comprising:

a bus;

bus devices, each bus device configured to assert a request signal to request the bus; and

an arbiter configured to mask or not to mask the request signal of a retried bus device depending upon whether the retried bus device is a multi-threaded device, wherein the request signal is not masked if the retried bus device is a multi-threaded device.

2. The computer system of claim 1, wherein the arbiter masks the request signal of a retried bus device if it is a single-threaded device.

3. The computer system of claim 1, further comprising:

a detector for determining if a bus device is multi-threaded.

4. The computer system of claim 3, wherein the detector compares a first bus transaction generated by the retried bus device with a second bus transaction generated by the retried bus device, the detector determining whether the retried bus device is a multi-threaded device based on the comparison.

5. The computer system of claim 3, further comprising:

a second bus, wherein the multi-threaded bus device includes a bridge connected between the first bus and the second bus.

6. The computer system of claim 1, further comprising:

a second bus; and

a bridge connected between the first and second buses.

7. The computer system of claim 6, wherein the bridge retries a bus device request which is targeted to the second bus.

8. The computer system of claim 7, wherein the bus device request targeted to the second bus includes a delayed request transaction.

9. The computer system of claim 7, wherein the second bus includes a PCI bus.

10. The computer system of claim 7, wherein the first bus includes a PCI bus.

11. The computer system of claim 1, wherein the bus includes a PCI bus.

12. The computer system of claim 1 further comprising additional devices, wherein the multi-threaded device is capable of generating requests on behalf of the additional devices.

13. The computer system of claim 12, wherein the multi-threaded device is capable of generating a request on behalf of one of the additional devices even though a prior request generated by the multi-threaded device on behalf of another one of the additional devices was retried.

14. A computer system comprising:

a bus;

a bus device capable generating a bus transaction on the bus;

a comparator for comparing a first bus transaction of a predetermined type associated with the bus device with a second bus transaction generated by the bus device to determine if the bus device is a multi-threaded device, wherein the bus device is determined to be the multi-threaded device if the second bus transaction differs from the first bus transaction.

15. The computer system of claim 14, further comprising:

a second bus, wherein the multi-threaded bus device includes a bridge connected between the first bus and the second bus.

16. The computer system of claim 14, further comprising:

a second bus, wherein the first and second bus transactions are targeted to the second bus.

17. The computer system of claim 16, wherein the first and second bus transactions include delayed request transactions.

18. The computer system of claim 16, wherein the second bus includes a PCI bus.

19. The computer system of claim 16, wherein the first bus includes a PCI bus.

20. The computer system of claim 14, wherein the first transaction of the predetermined type includes a transaction that has been retried.

21. A method of granting access to bus devices on a bus in a computer system, comprising:

each bus device asserting a request signal to request the bus;

masking or not masking the request signal of a retried bus device depending on whether the retried bus device is a multi-threaded device, wherein the recuest signal is not masked if the bus device is a multi-threaded device.

22. The method of claim 21, further comprising:

comparing a first bus transaction generated by a bus device with a second bus transaction generated by the bus device;

determining whether the bus device is a multi-threaded device based on the comparison.

23. The method of claim 21, wherein the computer system further includes a second bus, and wherein the multi-threaded bus device includes a bridge connected between the first bus and the second bus.

24. The method of claim 21, wherein the computer system further includes a second bus, the method further comprising:

retrying a bus device request which is targeted to the second bus.

25. The method of claim 24, wherein the bus device request targeted to the second bus includes a delayed request transaction.

26. The method of claim 24, wherein the second bus includes a PCI bus.

27. The method of claim 24, wherein the first bus includes a PCI bus.

28. The method of claim 21, wherein the bus includes a PCI bus.

29. A method of detecting a multi-threaded bus device on a bus in a computer system, comprising:

comparing a first bus transaction of a predetermined type associated with the bus device with a second bus transaction generated by the bus device; and

indicating the bus device as being a multi-threaded device based on the comparison, wherein the bus device is determined to be the multi-threaded device if the second bus transaction differs from the first bus transaction.

30. The method of claim 29, wherein the computer system further includes a second bus, and wherein the multi-threaded bus device includes a bridge connected between the first bus and the second bus.

31. The method of claim 29, wherein the computer system further includes a second bus, and wherein the first and second bus transactions are targeted to the second bus.

32. The method of claim 31, wherein the first and second bus transactions include delayed request transactions.

33. The method of claim 31, wherein the second bus includes a PCI bus.

34. The method of claim 31, wherein the first bus includes a PCI bus.

35. The method of claim 29, wherein the first bus transaction of the predetermined type includes a transaction that has been retried.

36. Apparatus for granting access to bus devices on a bus in a computer system, each bus device asserting a request signal to request the bus, the apparatus comprising:

a detector for determining if a bus device is multi-threaded; and

an arbiter masking or not masking the request signal of a retried bus device depending on whether the retried bus device is a multi-threaded device, wherein the request signal is not masked if the bus device is a multi-threaded device.

37. The apparatus of claim 36, wherein the arbiter masks the request signal of a retried bus device if it is a single-threaded device but does not mask the request signal if the retried bus device is a multi-threaded device.

38. The apparatus of claim 36, wherein the detector compares a first bus transaction generated by the retried bus device with a second bus transaction generated by the bus device, the detector determining whether the retried bus device is multi-threaded based on the comparison.

39. The apparatus of claim 36, wherein the bus includes a PCI bus.

40. The apparatus of claim 36, wherein the multi-threaded device is associated with additional devices, the multi-threaded device being capable of generating requests on behalf of the additional devices.

41. The computer system of claim 40, wherein the multi-threaded device is capable of generating a request on behalf of one of the additional devices even though a prior request generated by the multi-threaded device on behalf of another one of the additional devices was retried.

42. Apparatus for detecting a multi-threaded bus device on a bus in a computer system, wherein a bus device on the bus is capable of generating bus transactions, the apparatus comprising:

receiving circuitry for receiving the bus transactions; and

a comparator for comparing a first bus transaction of a predetermined type generated by the bus device with a second bus transaction generated by the bus device and delivering a signal indicating that the bus device is the multi-threaded device in response to the second bus transaction differing from the first bus transaction.

43. The apparatus of claim 42, wherein the bus includes a PCI bus.

44. A computer system comprising:

a bus;

bus devices, each bus device asserting a request signal to request the bus;

a detector for determining if a bus device is multi-threaded, wherein the detector compares a first bus transaction generated by the bus device with a second bus transaction generated by the bus device, the detector indicating the bus device as being a multi-threaded device if the first bus transaction is different from the second bus transaction; and

an arbiter, the arbiter masking the request signal of a bus device if the bus device has been retried and it is a single-threaded device, and the arbiter not masking the request signal of the bus device if the bus device has been retried but it is a multi-threaded device.

45. A computer system comprising:

a bus;

a bus device coupled to the bus that is configured to assert requests for the bus;

a decoder that compares information associated with a first retried request from the bus device with a second, subsequent request from the bus device; and

an arbiter that is configured not to mask the second request if the comparison indicates that the first and second requests have different sources.

46. The computer system of claim 45, further comprising additional devices, wherein the bus device is coupled to the additional devices and generates requests on behalf of the additional devices.

47. The computer system of claim 46, wherein the first request is generated on behalf of one of the additional devices and the second request is generated on behalf of another one of the additional devices.

48. The computer system of claim 47, further comprising a second bus, wherein the additional devices are coupled to the second bus and the bus device includes a bridge between the first and second buses.

49. A computer system comprising:

a bus;

a first bus device adapted to assert a request signal to request the bus;

a delayed transaction queue adapted to store at least a first delayed bus transaction associated with the first bus device; and

a comparator for comparing a retried bus transaction generated by the first bus device with the first delayed bus transaction to determine if the bus device is multi-threaded, wherein the bus device is determined to be the multi-threaded device if the second bus transaction differs from the first bus transaction; and

an arbiter configured to mask the request signal if the first bus device is not the multi-threaded device.