System and method for simulation of integrated hardware and software components

• US 6,052,524 A
• Filed: 05/14/1998
• Issued: 04/18/2000
• Est. Priority Date: 05/14/1998
• Status: Expired due to Term

• Current Assignee: Software Development Associates, Inc.
• Original Assignee: Software Development Associates, Inc.
• Inventors: Pauna, Mark R.
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): CHOI, KYLE JAEHUN
• Application Number:
  US09/079,448
• Time in Patent Office: 705 Days
• Field of Search: 395/500.4, 395/500.43, 395/500.42, 395/500.49, 395/500.05
• US Class Current: 703/22
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking

Abstract

A system and methods are provided to design, verify and develop simulated hardware and software components for a desired electrical device. The system includes a cycle-accurate simulator where X-number of simulator cycles is equivalent to Y-number of cycles on a simulated hardware component. The system further includes a simulator library for modeling and verifying hardware components of a desired electronic device. The simulator library includes built-in models and routines for simulating multiple internal hardware components. The simulator library is used with the cycle-accurate simulator. The system also includes a simulation Application Program Interface ("API") for allowing user-customized model and routines of internal and external hardware components to be used with the cycle-accurate simulator. The system can be used to design, verify and develop on-chip and off-chip components for a system-on-a-chip used in a desired electrical device. The methods provided include first method to simulate a requested operation for a simulated component far in the future with a fixed-length cycle counter by adjusting internal cycle counts in the cycle-accurate simulator for the requested operation and for the fixed-length cycle counter. A second method is used to send a not-ready response for a requested operation, when the requested operation takes longer than an estimated number of cycles in the cycle-accurate simulator. The system and methods allow for detecting access errors, bus faults, invalid address translations, privilege protection violations, alignment violations and other timing and behavior violations for simulated hardware and software components and the integration thereof.

Claims

1. A hardware-software design verification system, the system comprising:

a cycle-accurate simulator that simulates hardware and software components in a desired electronic device, wherein X-number of simulator cycles correspond to Y-number of cycles on a simulated hardware component, wherein the cycle-accurate simulator is event-driven, and events are used to determine timing behavior and interactions of simulated hardware and software components in the desired electronic device;

a simulator library including a plurality of built-in routines for modeling and verifying internal and external hardware components for a desired electronic device, wherein the simulator library allows internal and external hardware components to be modeled and verified with the plurality of built-in routines and wherein one or more of the plurality of built-in routines return a number of cycles executed on the cycle-accurate simulator during a simulated operation;

a simulator extension application programming interface that provides an interface to the plurality of built-in routines in the simulator, wherein the simulator application programming interface also allows external and internal hardware components to be modeled with user-customized routines used with the cycle-accurate simulator.

2. The system of claim 1 further comprising:

a graphical user interface, for providing inputs to, and receiving outputs from the cycle-accurate simulator.

3. The system of claim 1, wherein the internal hardware components are on-chip hardware components, and the external hardware components are off-chip hardware components for a system-on-a-chip being verified for the desired electronic device.

4. The system of claim 1, wherein the simulated hardware components include any of a central processing unit, memory, digital signal processor, memory management unit, cache, bus, timer, or a universal asynchronous receiver transmitter.

5. The system of claim 1, wherein the simulator library includes built-in routines for simulating any of M-Core, PowerPC, CPU32, CPU32+ or 68000 families of central processing units.

6. The system of claim 1, wherein the cycle-accurate simulator includes an instruction timing mode that determines the total number of cycles required to execute a general operation, but does not simulate the order of timing of individual operations that make up the general operation.

7. The system of claim 1, wherein the simulator library comprises a plurality of routines on a computer readable medium including:

a routine for setting a clock for a simulated component to a new clock speed;

a routine for coordinating between a simulated component clock and a cycle-accurate simulator clock;

a routine for handling events that occur before or during a current clock cycle;

a routine for sending a notification of changes in registers during a simulated operation;

a routine for setting one or more individual sub-components of a simulated hardware component;

a routine to lock and unlock a simulated bus;

a routine to set operation of a simulated component in a low power mode;

a routine for setting an event to occur at a desired cycle on the cycle-accurate simulator;

a routine for changing interrupt vectors and interrupt priority levels for a simulated component;

a routine for accessing a desired register on a simulated component; and

a routine to add a simulated register to a simulated component.

8. The system of claim 1 wherein X-number of cycles of simulator cycles on the cycle-accurate simulator is greater than Y-number of cycles on a simulated hardware component.

9. A hardware-software design verification system, the system comprising:

a cycle-accurate simulator, for simulating hardware and software components for a system-on-a-chip, wherein X-number of simulator cycles correspond to Y-number of cycles on a simulated hardware component, wherein the cycle-accurate simulator is event-driven, and events are used to determine timing behavior and interactions of simulated hardware and software components in the system-on-a-chip;

a simulator library, for modeling and verifying on-chip and off-chip hardware components for a system-on-a-chip, wherein the simulator library allows on-chip and off-chip hardware components to be modeled with a plurality of built-in routines used with the cycle-accurate simulator and wherein one or more of the plurality of built-in routines return a number of cycles executed on the cycle accurate simulator during a simulated operation;

a simulator application programming interface, for modeling and verifying hardware components for a system-on-a-chip, wherein the simulator application programming interface allows on-chip and off-chip hardware components to be modeled with user-customized routines used with the cycle-accurate simulator.

10. A method for hardware-software verification in a simulator, the method comprising the steps of:

(a) receiving a request for a simulated operation from a simulated hardware component on a cycle-accurate simulator, wherein the requested simulated operation requests X-number of cycles on the cycle-accurate simulator and the cycle-accurate simulator has a cycle-counter of a fixed length for counting Y-number of cycles, wherein Y is less than X;

(b) setting an event to occur at X-number of cycles on the cycle-accurate simulator;

(c) executing Z-number of cycles on the cycle-accurate simulator, wherein the Z-number of cycles is less than Y-number of cycles and the Z-number of cycles are counted in the cycle-counter;

(d) determining whether X-Z number of cycles remaining for the event can be executed in Y-Z number of cycles remaining in the cycle-counter, and if not,

(e) subtracting N-number of cycles from X-number of cycles to adjust the number of cycles remaining for the event, thereby creating an adjusted event;

(f) subtracting M-number of cycles from the Y-Z number of cycles remaining in the cycle counter, thereby creating an adjusted cycle-counter count corresponding to the adjusted event;

(g) repeating steps (c), (d), (e) and (f) until the number of cycles remaining to reach the adjusted event can be executed within the Y-Z number of cycles remaining in the adjusted cycle-counter count.

11. The method of claim 10 wherein steps (a)-(g) are stored on a computer readable medium.

12. The method of claim 10 wherein the event is an interrupt.

13. The method of claim 10 wherein the N-number of cycles is equal to the M-number of cycles.

14. The method of claim 10 wherein the N-number of cycles is not equal to the M-number of cycles.

15. A method for hardware-software verification in a simulator, the method comprising the steps of:

receiving a request for a simulated operation in a cycle-accurate simulator from a simulated component;

determining on the cycle accurate simulator X-number of cycles needed to complete the requested simulated operation;

setting a first event at X-number of cycles on the cycle-accurate simulator;

executing X-number of cycles on the cycle-accurate simulator;

determining whether the requested simulated operation is complete at the first event after X-number of cycles,

and if not,

determining on the cycle-accurate simulator Y-number of cycles needed to complete the requested simulated operation, wherein Y-number of cycles is a minimum number of cycles needed to complete the requested simulated operation;

setting a second event at Y-number of clock cycles; and

returning a not-ready result for the requested simulated operation to the simulated component including the Y-number of cycles.

16. The method of claim 15 wherein the method steps are stored on a computer readable medium.

17. The method of claim 15 further comprising:

determining whether the requested simulated operation is complete after X-number of cycles, and if so,

returning results of the requested simulated operation, wherein the results include an actual number of cycles required to complete the requested simulated operation.

18. The method of claim 15 wherein the simulated component is any of a simulated hardware component or a simulated software component.

19. The method of claim 15 wherein the event is an interrupt.

20. The method of claim 15 further comprising:

executing Y-number of cycles on the cycle-accurate simulator;

determining whether the requested simulated operation is complete at the second event after Y-number of cycles, and if so

returning an actual number of cycles required to complete the requested simulated operation to the simulated component.

21. A computer readable medium having stored therein a set of built-in general purpose routines for implementing a simulator library used for simulating hardware and software components on a cycle-accurate simulator, the computer readable medium comprising:

a routine for setting a clock for a simulated component to a new clock speed;

a routine for coordinating between a simulated component clock and a cycle-accurate simulator clock;

a routine for handling events that occur before or during a current clock cycle;

a routine for sending a notification of changes in registers during a simulated operation; and

a routine for setting one or more individual sub-components of a simulated hardware component.

22. The computer readable medium of claim 21 further comprising:

a routine to lock and unlock a simulated bus; and

a routine to set operation of a simulated component in a low power mode.

23. A computer readable medium having stored therein a set of built-in call-back routines for implementing a simulator library used for simulating hardware and software components on a cycle-accurate simulator, the computer readable medium comprising:

a routine for setting an event to occur at a desired cycle for a simulated component on the cycle-accurate simulator;

a routine for changing interrupt vectors and interrupt priority levels for a simulated component on the cycle-accurate simulator for a desired event;

a routine for accessing a desired register on a simulated component on the cycle-accurate simulator after an event has occurred; and

a routine for adding a simulated register to a simulated component on the cycle-accurate simulator for a desired event.

24. A method for hardware-software verification in a simulator, the method comprising the steps of:

receiving a request for a simulated operation on a cycle-accurate simulator from a simulated component, wherein the requested simulated operation needs X-number of cycles on the cycle-accurate simulator to complete the requested simulated operation; and

returning a result to the simulated component, wherein the result includes Y-number of cycles, an actual number of cycles on the cycle-accurate simulator used to complete the requested simulated operation.

25. The method of claim 24 wherein the method steps are stored on a computer readable medium.

26. A method for hardware verification in a cycle-accurate simulator, the method comprising the steps of:

receiving a request for a simulated operation from a simulated hardware component on a cycle-accurate simulator, wherein the requested simulated operation on the simulated hardware component requests X-number of cycles on the cycle-accurate simulator and the cycle-accurate simulator has a cycle-counter of a fixed length for counting Y-number of cycles, wherein Y is less than X; and

periodically adjusting the cycle-counter and the X-number of cycles by a pre-determined value to allow the cycle-accurate simulator with the cycle-counter of a fixed length for counting Y-number of cycles to provide a requested simulated operation for the simulated hardware component request at X-number of cycles, wherein Y is less than X.

27. The method of claim 26 wherein the method steps are stored on a computer readable medium.