Method and apparatus in a packet routing switch for controlling access at different data rates to a shared memory

• US 6,052,738 A
• Filed: 06/30/1997
• Issued: 04/18/2000
• Est. Priority Date: 06/30/1997
• Status: Expired due to Term

• Current Assignee: Oracle America, Inc. (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Muller, Shimon, Pham, Binh, Berg, Curt
• Primary Examiner(s): RINEHART, MARK H
• Assistant Examiner(s): RINEHART, MARK H
• Application Number:
  US08/885,154
• Time in Patent Office: 1,023 Days
• Field of Search: 370/401, 370/402, 370/415, 370/416, 370/420, 711/130, 711/131, 711/147, 711/149, 711/150, 711/151, 711/152, 711/163, 711/168, 365/220, 365/230.05, 365/230.06, 365/230.08, 395/200.8, 395/200.43, 395/300, 395/291, 710/120, 710/111, 709/250, 709/213
• US Class Current: 709/250
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234

Abstract

A method and apparatus for controlling access to a shared memory in a network system is described. The apparatus includes at least one fast port interface circuit, each comprising a fast input port interface configured to sequentially receive data, address, and command information from a network client at a first data rate in segments of a first width. Each fast input port interface comprises a fast interface register configured to temporarily store the data and address information. Each fast input port interface further comprises a command decode circuit configured to receive the command information and, in response, sequentially store the segments of data and address information in the fast interface register until the fast interface register is full, the fast interface register further configured to be read out in parallel to the shared memory. The apparatus also includes at least one slow port interface circuit, each configured to receive data, address, and command information from a network client at a second data rate in segments of the first width and transmit the data, address, and command information to a storage circuit that is shared among the slow port interface circuits. The shared storage circuit comprises a plurality of slow interface registers, wherein the segments of data are sequentially stored in one of the slow interface registers at the same time the contents of another slow interface register are read out in parallel to the shared memory.

Claims

1. An apparatus for controlling access to a shared memory in a network system, comprising:

at least one fast port interface circuit, each comprising a fast input port interface configured to sequentially receive data, address, and command information from a network client at a first data rate in segments of a first width, each fast input port interface comprising;

a fast interface register configured to temporarily store the data and address information; and

a command decode circuit configured to receive the command information and, in response, sequentially store the segments of data and address information in the fast interface register until the fast interface register is full, the fast interface register further configured to be read out in parallel to the shared memory; and

at least one slow port interface circuit, each configured to receive data, address, and command information from a network client at a second data rate in segments of the first width and transmit the data, address, and command information to a storage circuit that is shared among the slow port interface circuits, the shared storage circuit comprising a plurality of slow interface registers, wherein the segments of data are sequentially stored in one of the slow interface registers at the same time the contents of another slow interface register are read out in parallel to the shared memory.

2. The apparatus of claim 1, wherein the slow port interface circuit further comprises an output port interface including a plurality of output interface registers, wherein one of the output interface registers is configured to receive data in parallel from the shared memory at the same time as the contents of another one of the output interface registers are output to an output port in sequential segments of the first width.

3. The apparatus of claim 2, wherein the fast port interface circuit further comprises the output port interface.

4. The apparatus of claim 3, further comprising a scheduling circuit coupled to the fast port interface circuit and to the shared storage circuit that receives requests for read and write operations to the shared memory, the scheduling circuit configured to schedule the operations such that all read operations are complete before write operations are completed.

5. The apparatus of claim 4, further comprising a memory controller coupled to the scheduling circuit and to the shared memory, the memory controller configured to receive a memory address from the scheduling circuit and issue commands to the shared memory.

6. The apparatus of claim 3, wherein the output port interface further comprises a command decode circuit configured to receive and decode the command information and, in response, assemble a read address in a read address register and generate a read request to the shared memory.

7. The apparatus of claim 6, wherein the output port interface further comprises output data registers coupled to the shared memory and a flow control circuit, wherein the output data registers receive data from the shared memory and the data is output from one of the output data registers to an output port in segments of the first width and the flow control circuit issues a read wait signal to the output port when data is not ready in an output data register.

8. The apparatus of claim 7, further comprising a read pipe that receives a port identification of an output port requesting a read and outputs a read tag to the flow control circuit that indicates a port to which data from the output data registers is sent.

9. The apparatus of claim 1, wherein the first width is sixteen bits and wherein a width of the fast interface register and a width of each slow interface register are of a second width eight times the first width.

10. The apparatus of claim 6, wherein the output port interface comprises multiple read address registers, including a current address register configured to store a current read address and a next address register configured to store a next packet address.

11. The apparatus of claim 10, wherein the current address register is further configured to be incremented for each write of data from a current packet occurring to the shared memory.

12. The apparatus of claim 11, further comprising a multiplexor configured to select an address from one of the multiple read registers to be transmitted to the shared memory.

13. The apparatus of claim 10, wherein the first width is sixteen bits, the data buffer registers comprise 128 bits and a read address addresses a packet comprising multiple 128-bit data words.

14. The apparatus of claim 1, wherein the fast input port interface further comprises a flow control circuit coupled to the shared memory configured to receive a full signal from the command decode circuit when the fast interface register is full and, in response, transmit a write wait signal to a port requesting a write operation.

15. The apparatus of claim 14, wherein the fast input port interface further comprises an address register and a tag register configured to store an address and a tag associated with data in the fast interface register and configured to be loaded according to a signal from the command decode circuit in sequential segments of the first width.

16. In a network switching element, an apparatus for controlling access to a shared memory of the switching element, comprising:

a fast port interface circuit configured to receive segments of data from the network at a fast data rate into a register;

a second level arbiter circuit coupled to the fast port interface circuit wherein, when the register is filled contents of the register are transmitted in parallel to the second level arbiter circuit; and

a slow port interface circuit configured to transfer segments of data from the network at a slow data rate; and

a first level arbiter circuit coupled to the slow port interface circuit to receive the segments of data, wherein access to the first level arbiter is granted to the slow port interface circuit on a round-robin basis.

17. The apparatus of claim 16, wherein the second level arbiter circuit is further coupled to the first level arbiter circuit and to the shared memory such that data segments received by the first level arbiter circuit are transmitted to the second level arbiter circuit before being stored in the shared memory.

18. The apparatus of claim 17, wherein each of the fast port interface circuit and the slow port interface circuit comprise an output port interface including a plurality of output interface registers, wherein one of the output interface registers is configured to receive data in parallel from the shared memory at the same time as the contents of another one of the output interface registers are output to an output port in sequential segments.

19. A method of controlling access to a shared memory in a network switching circuit by network clients operating at different data rates, comprising the steps of:

receiving segments of data at a fast data rate;

storing the segments of data in a register;

when the register is filled, writing contents of the register to a second level arbiter circuit;

transferring the segments of data from the second level arbiter circuit to the shared memory;

receiving segments of data at a slow data rate;

transferring the segments of data to a first level arbiter circuit; and

transferring the segments of data from the first level arbiter circuit to the second level arbiter circuit.

20. The method of claim 19, further comprising the steps of:

granting access to the second level arbiter to a network client operating at the slow data rate on a round-robin basis;

sequentially storing segments of data in an unfilled register in the first level arbiter circuit; and

simultaneously reading out in parallel all segments stored in a filled register in the first level arbiter circuit to the shared memory.

21. The method of claim 20, further comprising the steps of:

receiving a data word from the shared memory and storing the data word in a first output register;

transferring segments of the first data word to the network; and

simultaneously receiving a next data word from the shared memory and storing the next data word in a second output register.

22. The method of claim 21, further comprising the steps of:

receiving a read request signal from an output port;

responding to the read request by reading a data word from the shared memory to one of the first output register or the second output register; and

asserting a read wait signal to the output port so that while the read wait signal is generated, no read request signal is generated by the output port.