Method and apparatus for changing the number of access slots into a memory

• US 6,052,751 A
• Filed: 12/18/1997
• Issued: 04/18/2000
• Est. Priority Date: 02/14/1997
• Status: Expired due to Term

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices SDN Berhad (Advanced Micro Devices, Inc.)
• Inventors: Erimli, Bahadir, Runaldue, Thomas J.
• Primary Examiner(s): Ray, Gopal C.
• Application Number:
  US08/992,814
• Time in Patent Office: 852 Days
• Field of Search: 710/107, 710/131, 710/132, 710/33, 710/34, 710/35, 710/62, 710/101, 710/100, 710/117, 710/129, 710/45, 713/501, 713/600, 711/100, 340/825, 340/825.83, 340/827, 326/38, 370/375, 370/402, 370/902, 370/911, 370/912
• US Class Current: 710/107
• CPC Class Codes: G06F 13/1605 based on arbitration arbitration in handling access to a common bus or bus system G06F13/36
• CPC Class Codes: G06F 13/24 using interrupt G06F13/32 takes precedence
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: H04L 12/1863 comprising mechanisms for improved reliability, e.g. status reports arrangements for detecting or preventing errors by carrying supervisory signal the return channel H04L1/16
• CPC Class Codes: H04L 12/4641 Virtual LANs, VLANs, e.g. virtual private networks [VPN] LAN interconnection over a bridge based backbone H04L12/462; encapsulation techniques H04L12/4633; routing of packets H04L45/00; packet switches H04L49/00; virtual private networks for security H04L63/0272
• CPC Class Codes: H04L 12/4645 Details on frame tagging routing of packets H04L45/00; support for virtual LAN H04L49/354
• CPC Class Codes: H04L 12/467 Arrangements for supporting untagged frames, e.g. port-based VLANs
• CPC Class Codes: H04L 41/0213 Standardised network management protocols, e.g. simple network management protocol [SNMP]
• CPC Class Codes: H04L 47/50 Queue scheduling
• CPC Class Codes: H04L 47/6225 Fixed service order, e.g. Round Robin
• CPC Class Codes: H04L 49/103 using a shared central buffer; using a shared memory
• CPC Class Codes: H04L 49/201 Multicast operation; Broadcast operation
• CPC Class Codes: H04L 49/25 Routing or path finding in a switch fabric
• CPC Class Codes: H04L 49/255 Control mechanisms for ATM switching fabrics
• CPC Class Codes: H04L 49/30 Peripheral units, e.g. input or output ports
• CPC Class Codes: H04L 49/3009 Header conversion, routing tables or routing tags
• CPC Class Codes: H04L 49/3027 Output queuing
• CPC Class Codes: H04L 49/3054 Auto-negotiation, e.g. access control between switch gigabit interface connector [GBIC] and link
• CPC Class Codes: H04L 49/351 for local area network [LAN], e.g. Ethernet switches
• CPC Class Codes: H04L 49/354 for supporting virtual local area networks [VLAN]
• CPC Class Codes: H04L 49/40 : Constructional details, e.g. power supply, mechanical construction or backplane
• CPC Class Codes: H04L 49/50 : Overload detection or protection within a single switching element
• CPC Class Codes: H04L 49/552 : by ensuring the integrity of packets received through redundant connections
• CPC Class Codes: H04L 49/555 : Error detection
• CPC Class Codes: H04L 49/90 : Buffering arrangements
• CPC Class Codes: H04L 49/901 : using storage descriptor, e.g. read or write pointers
• CPC Class Codes: H04L 49/9047 : including multiple buffers, e.g. buffer pools
• CPC Class Codes: H04L 49/9063 : Intermediate storage in different physical parts of a node or terminal
• CPC Class Codes: H04L 49/9073 : Early interruption upon arrival of a fraction of a packet
• CPC Class Codes: H04L 49/9078 : using an external memory or storage device
• CPC Class Codes: H04L 49/9084 : Reactions to storage capacity overflow
• CPC Class Codes: H04Q 2213/1316 : Service observation, testing
• CPC Class Codes: H04Q 2213/13162 : Fault indication and localisation
• CPC Class Codes: H04Q 3/54591 : Supervision, e.g. fault localisation, traffic measurements, avoiding errors, failure recovery, monitoring, statistical analysis

Abstract

A scalable multiport switch that receives and transmits data through a plurality of ports is provided with a plurality of internal buses, an external memory interface, and a slot manager. The external memory interface is coupled to the internal buses and has an external memory port for coupling the external memory interface to an external memory. The slot manager schedules access to the external memory through the internal buses and the external memory interface in a series of time slots. Each slot consists of m clock cycles to transfer n bytes of data. The slot manager is operable at a selectable one of multiple frequencies, the operating frequency of the slot manager being selected to match an operating frequency of the external memory. The slot manager increases the number of slots per given period of time with increasing operating frequency of the slot manager, but maintains the number of clock cycles per slot constant, thereby providing greater access to other sources of data.

Claims

1. A scalable multiport switch that receives and transmits data through a plurality of ports, the switch comprising:

a plurality of internal buses;

an external memory interface coupled to the internal buses and having an external memory port for coupling the external memory interface to an external memory; and

a slot manager that manages access to an external memory through the internal buses and the external memory interface, the slot manager scheduling access in a series of time slots, with each slot consisting of m clock cycles to transfer n bytes of data, wherein the slot manager is operable at a selectable one of multiple frequencies, the operating frequency of the slot manager being selected to match an operating frequency of the external memory, the slot manager increasing the number of slots per given period of time with increasing operating frequency of the slot manager and maintaining the number of clock cycles per slot constant.

2. The switch of claim 1, wherein the operating frequency of the slot manager is selectable between 80 MHz, 100 MHz and 120 MHz.

3. The switch of claim 2, wherein the number m of clock cycles in each slot is 16.

4. The switch of claim 3, wherein the buses include a data bus that carries data between the multiple ports of the switch and the external memory interface, a control bus that carries control information, and an external connection bus that carries information between the switch and devices external to the switch.

5. The switch of claim 4, wherein the number of slots per given period of time is 4 slots when the slot manager is selected to have an operating frequency of 80 MHz, 5 slots when the slot manager is selected to have an operating frequency of 100 MHz, and 6 slots when the slot manager is selected to have an operating frequency of 120 MHz.

6. The switch of claim 5, wherein 4 slots in the given period of time are substantially reserved for access by the data bus, the slot manager including means for assigning slots unused by the data bus to either the control bus or the external connection bus.

7. The switch of claim 6, wherein the fifth slot in the given period of time when the operating frequency of the slot manager is at 100 MHz or 120 MHz is reserved for access by at least one of the control bus and the external connection bus.

8. The switch of claim 7, wherein the sixth slot in the given period of time when the operating frequency of the slot manager is at 120 MHz is reserved for access by at least one of the control bus and the external connection bus.

9. The switch of claim 8, wherein the slots in a first one of consecutive given periods of time are dedicated to write accesses to the external memory and the slots in a second one of consecutive given periods of time are dedicated to read accesses to the external memory.

10. The switch of claim 9, wherein each slot is divided into two transfers.

11. A method of scheduling access of buses internal to a network switch to a memory that is external to the switch, the method comprising the steps of:

determining the operating frequency of an external memory connected to the switch;

scheduling access of the buses in a series of time slots, with each slot consisting of m clock cycles to transfer n bytes of data; and

setting the number of slots per given period of time in accordance with the operating frequency of the external memory and maintaining the number of clock cycles per slot constant, such that the number of slots per given period of time increase with increasing operating frequency of the external memory.

12. The method of claim 11, wherein the buses include a data bus that carries data, a control bus that carries control information and an external connection bus that carries information between the switch and devices external to the switch, and further comprising substantially reserving a given number x of slots in the given period of time for access by the data bus, and assigning slots unused by the data bus to either the control bus or the external connection bus.

13. The method of claim 12, wherein the number of slots per given period of time is 4 slots when the external memory has an operating frequency of 80 MHz, 5 slots when the external memory has an operating frequency of 100 MHz, and 6 slots when the external memory has an operating frequency of 120 MHz.

14. The method of claim 13, further comprising assigning the fifth slot in the given period of time when the operating frequency of the external memory is at 100 MHz or 120 MHz for access by at least one of the control bus and the external connection bus.

15. The method of claim 14, further comprising assigning the sixth slot in the given period of time when the operating frequency of the slot manager is at 120 MHz for access by at least one of the control bus and the external connection bus.