Fault tolerant data bus
First Claim
1. A data bus system comprising:
- a processor having an application memory;
a bus interface controller operatively connected to said processor and said application memory;
a data bus including at least one data line wherein data is transmitted in a plurality of time frames wherein each of said time frames is divided into a plurality of time slots; and
a time table operatively connected to said bus interface controller for mapping a plurality of said time slots into a data transmission channel wherein said channel in each of said time frames is assigned to said bus interface controller for transmission of data from said bus interface controller to said channel on said data bus.
1 Assignment
0 Petitions
Accused Products
Abstract
A fault tolerant bus architecture and protocol for use in applications wherein data must be handled with a high degree of integrity and in a fault tolerant manner. As applied to an integrated flight hazard avoidance system, the system is constructed of two or more microprocessor-driven modules that generate data, two independent bus interface controllers per module, and an inter-module backplane data bus that links each module. The system allows comparison of identical data from multiple sources. If invalid data is detected, the system either passes the correct data copy or generates a system fault message. The bus architecture utilizes a distributed synchronization protocol, and does not require a master synchronization source.
-
Citations
20 Claims
-
1. A data bus system comprising:
-
a processor having an application memory; a bus interface controller operatively connected to said processor and said application memory; a data bus including at least one data line wherein data is transmitted in a plurality of time frames wherein each of said time frames is divided into a plurality of time slots; and a time table operatively connected to said bus interface controller for mapping a plurality of said time slots into a data transmission channel wherein said channel in each of said time frames is assigned to said bus interface controller for transmission of data from said bus interface controller to said channel on said data bus. - View Dependent Claims (2, 3)
-
-
4. A data bus system comprising:
-
a plurality of nodes each including a processor having an application memory; a first bus interface controller for each of said nodes operatively connected to said processor and said application memory for that node; a data bus including at least one data line wherein data is transmitted in a plurality of time frames wherein each of said time frames is divided into a plurality of time slots; a time table operatively connected to each of said first bus interface controllers for mapping a plurality of said time slots in each of said frames into a data transmission channel wherein each of said channels is assigned to a predetermined one of said nodes for transmission of data to and from said application memory in said predetermined node through said first bus interface controller to and from said channel on said data bus; and a space table operatively connected to each of said first bus interface controllers for mapping said channel assigned to that node into a predetermined data location in said application memory for that node. - View Dependent Claims (5, 6, 7, 8, 9)
-
-
10. A data bus system comprising:
-
a data bus including at least one data line wherein data is transmitted in a plurality of time frames wherein each of said time frames is divided into a plurality of time slots; a plurality of nodes each including a first and a second processor for executing application programs each having an independent application memory and an independent clock wherein the data resulting from said programs is transmitted to said application memories by each of said processors; a pair of bus interface controllers located in each of said nodes and individually connected one to each of said application memories in each of said nodes including means for receiving said data from said data bus wherein said bus interface controllers in each node are connected by a data exchange line; a time table operatively connected to each of said bus interface controllers for mapping a plurality of said time slots in each of said frames into a data transmission channel wherein each of said channels is assigned to a predetermined one of said nodes for transmission of data to and from said application memory through its associated bus interface controller to and from said channel on said data bus; comparison means located in said bus interface controllers for exchanging said data received from each said application memory over said data exchange line and comparing said data in each of said bus interface controllers; and transmission means associated with each of said bus interface controllers and responsive to said time table for transmitting said data to said data lines if said comparison means indicates said data is equivalent. - View Dependent Claims (11, 12)
-
-
13. A data bus system comprising:
-
a data bus including at least one data line wherein data is transmitted in a plurality of time frames wherein each of said time frames is divided into a plurality of time slots; a plurality of nodes each including a first and a second processor for executing different application programs independently wherein each of said first and second processors is operatively connected to a separate independent application memory and a separate independent clock wherein the data resulting from said programs is transmitted to said application memories by each of said processors; a pair of bus interface controllers located in each of said nodes and individually connected one to each of said application memories in each of said nodes including means for transmitting said data to and receiving said data from said data bus; and a time table operatively connected to each of said bus interface controllers for mapping a plurality of said time slots in each of said frames into a data transmission channel wherein each of said channels is assigned to a predetermined one of said nodes for transmission of data to and from said application memory through its associated bus interface controller to and from said channel on said data bus.
-
-
14. A method of transmitting data over a data bus between a plurality of nodes wherein each of the nodes includes at least one processor, comprising the steps of:
-
transmitting the data on the data bus in a plurality of time slots divided into a plurality of channels wherein each of said channels is assigned to one of the nodes; selectively receiving a first portion of said data in a first of said channels in a first of said nodes having two of the processors by a pair of bus interface controllers located in said first node wherein each of said bus interface controllers includes a time table defining said first channel containing said first portion of said data; and transferring said first portion of said data from said bus interface controllers to a pair of application memories each associated with the processors in said first node wherein a pair of space tables, each associated with one of said bus interface controllers defines the location in said application memories into which said first portion of said data is to be transferred. - View Dependent Claims (15, 16, 17, 18, 19)
-
-
20. A method of transmitting data over a data bus between a plurality of nodes wherein each of the nodes includes at least one processor, comprising the steps of:
-
transmitting the data on the data bus in a plurality of time slots divided into a plurality of channels wherein each of said channels is assigned to one of the nodes; selectively receiving a first portion of said data in a first of said channels in a first of said nodes having one of the processors by a pair of bus interface controllers located in said first node wherein each of said bus interface controllers includes a time table defining said first channel containing said first portion of said data; transferring said first portion of said data from said bus interface controllers to an application memory associated with the processor in said first node wherein a pair of space tables, each associated with one of said bus interface controllers defines the location in said application memories into which said first portion of said data is to be transferred; and comparing said first portion of said data in said bus interface controllers prior to transferring it to said application memory.
-
Specification