System and method for remapping defective memory locations

• US 6,052,798 A
• Filed: 07/01/1998
• Issued: 04/18/2000
• Est. Priority Date: 11/01/1996
• Status: Expired due to Term

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micro Electronics Incorporated
• Inventors: Jeddeloh, Joseph
• Primary Examiner(s): Beausoliel, Jr., Robert W.
• Assistant Examiner(s): Baderman, Scott T.
• Application Number:
  US09/108,572
• Time in Patent Office: 657 Days
• Field of Search: 395/182.06, 395/182.03, 395/183.18, 371/10.2, 371/10.3, 371/21.6
• US Class Current: 714/6.13
• CPC Class Codes: G11C 29/70 Masking faults in memories by using spares or by reconfiguring
• CPC Class Codes: G11C 29/76 using address translation or modifications

Abstract

A computer system includes a memory requester that interfaces with a memory module that includes memory portions. An error map that identifies the defective memory portions of the memory module is created and stored in the computer system. Using the error map, a remapping table that maps each of the defective memory portions to a non-defective memory portion in the memory module is created and then stored. In response to receiving from the memory requester a request for access to a requested memory portion of the memory module, a determination is made from the error map whether the requested memory portion is one of the defective memory portions. If the error map indicates that the requested memory portion is one of the defective memory portions, then a determination is made from the remapping table the non-defective memory portion to which the requested memory portion is mapped. The non-defective memory portion is accessed if the error map indicates that the requested memory portion is defective, and the requested memory portion is accessed if the error map does not indicate that the requested memory portion is defective.

Claims

1. A computer memory module for storing data and instructions for use by a computer system having a memory controller for controlling the memory module, the memory module comprising:

a volatile memory block having a plurality of volatile memory portions at least one of which may be defective;

a nonvolatile memory block having an error map that includes an error tag for each of the defective volatile memory portions, the error tag indicating that the volatile memory portion is defective, the error map enabling the memory controller to determine whether a requested volatile memory portion is one of the defective volatile memory portions so that the memory controller can access a non-defective volatile memory portion in response to receiving a request for the requested volatile memory portion; and

a remapping table included in the volatile memory block, the remapping table being created from the error map to map each of the defective volatile memory portions to a non-defective volatile memory portion in the volatile memory block so that a request for access to the defective volatile memory portion can be directed to the non-defective volatile memory portion.

2. The computer memory module of claim 1 wherein the remapping table is created by the memory controller from the error map and then stored in the volatile memory block by the memory controller.

3. The computer memory module of claim 1 wherein each of the defective volatile memory portions comprise four kilobyte blocks of memory locations in the volatile memory block.

4. The computer memory module of claim 1 wherein the error map includes a tag bit for each volatile memory portion, each tag bit being of a first logic value if a memory portion associated with the tag bit is defective and being of a second logic value if the memory portion associated with the tag bit is non-defective, the error tag being the tag bit of the first logic value.

5. A computer system for servicing a memory access request from a memory requester, comprising:

a memory module having a volatile memory block with a plurality of volatile memory portions at least one of which may be defective, the memory module including a nonvolatile memory block that stores error information that identifies each of the defective volatile memory portions as being defective; and

a memory controller coupled to the memory module, the memory controller comprising;

an error map created by the memory controller retrieving the error information from the nonvolatile memory block, the error map having an error tag for each defective volatile memory portion, the error tag indicating that the volatile memory portion is defective; and

a request processor that, in response to the memory access request, determines from the error map whether the requested volatile memory portion is defective and if the requested volatile memory portion is defective, directs the memory access request to a non-defective volatile memory portion of the volatile memory block rather than to the requested volatile memory portion.

6. The computer system of claim 5 wherein the memory module comprises a remapping table that maps each of the defective volatile memory portions to a non-defective volatile memory portion in the volatile memory block so that, in response to a request for access to the requested defective volatile memory portion, the memory controller uses the remapping table to access the non-defective volatile memory portion to which the requested defective volatile memory portion is mapped.

7. The computer system of claim 6 wherein the remapping table is created by the memory controller from the error map and then stored in the volatile memory block by the memory controller.

8. The computer system of claim 5 wherein each of the defective volatile memory portions comprise four kilobyte blocks of memory locations in the volatile memory block.

9. The computer system of claim 5 wherein the error map includes a tag bit for each volatile memory portion, each tag bit being of a first logic value if a memory portion associated with the tag bit is defective and being of a second logic value if the memory portion associated with the tag bit is non-defective, the error tag being the tag bit of the first logic value.

10. A memory controller for servicing a memory access request directed to a memory module from a memory requester, the memory module having a plurality of volatile memory portions at least one of which may be defective, the memory module further including a nonvolatile memory block that stores error information that identifies each defective volatile memory portion, the memory controller comprising:

a remapping processor that retrieves the error information from the nonvolatile memory block;

an error map having an error tag for each defective volatile memory portion, the error tag indicating that the volatile memory portion is defective, the error map being created from the error information retrieved by the remapping processor; and

a request processor that, in response to the memory access request, determines from the error map whether the requested volatile memory portion is defective and if the requested volatile memory portion is defective, directs the memory access request to a non-defective volatile memory portion of the memory module rather than to the requested volatile memory portion.

11. The memory controller of claim 10, further comprising a remapping processor that creates a remapping table based on the error map, the remapping table mapping each of the defective volatile memory portions to a non-defective volatile memory portion in the memory module, wherein the request processor employs the remapping table to direct the memory access request to the non-defective volatile memory portion of the memory module rather than to the requested volatile memory portion when the requested volatile memory portion is defective.

12. The memory controller of claim 10 wherein each of the defective volatile memory portions comprises four kilobyte blocks of memory locations in the memory module.

13. The memory controller of claim 10 wherein the error map includes a tag bit for each volatile memory portion, each tag bit being of a first logic value if a memory portion associated with the tag bit is defective and being of a second logic value if the memory portion associated with the tag bit is non-defective, the error tag being the tag bit of the first logic value.

14. A computer system for servicing memory access requests, comprising:

a memory module having a plurality of memory portions at least one of which may be defective, the memory module also including a remapping data structure that maps any defective memory portions of the memory module to respective non-defective memory portions of the memory module; and

a memory controller coupled to the memory module, the memory controller comprising;

an error map identifying which memory portions of the memory module are defective; and

a request processor that, in response to a memory access request, determines from the error map whether the requested memory portion is defective and if the requested memory portion is defective, determines from the remapping data structure the non-defective memory portion to which the defective memory portion is mapped, and directs the memory access request to the non-defective memory portion rather than to the requested memory portion.

15. The computer system of claim 14 wherein the memory module comprises:

a volatile memory block that includes the defective and non-defective memory portions,

a nonvolatile memory block that stores error information that identifies each of the defective memory portions as being defective, the error map stored in the memory controller being based on the error information stored in the nonvolatile memory block.

16. The computer system of claim 14 wherein the error map includes a tag bit for each of the memory portions, each tag bit being of a first logic value if a memory portion associated with the tag bit is defective and being of a second logic value if the memory portion associated with the tag bit is non-defective.