Process for filling deep trenches with polysilicon and oxide

• US 6,054,365 A
• Filed: 07/13/1998
• Issued: 04/25/2000
• Est. Priority Date: 07/13/1998
• Status: Expired due to Term

• Current Assignee: Infineon Technologies Americas Corp. (Infineon Technologies AG)
• Original Assignee: International Rectifier Corporation (Infineon Technologies AG)
• Inventors: Lizotte, Steven C.
• Primary Examiner(s): DANG, TRUNG Q
• Application Number:
  US09/114,546
• Time in Patent Office: 652 Days
• Field of Search: 438/430, 438/431, 438/432, 438/435, 438/437, 438/424, 438/928, 438/977
• US Class Current: 438/430
• CPC Class Codes: H01L 21/763 Polycrystalline semiconductor regions H01L21/76264 takes precedence
• CPC Class Codes: Y10S 438/928 Front and rear surface processing
• CPC Class Codes: Y10S 438/977 Thinning or removal of substrate

Abstract

A process for etching and filling a trench prevents the top opening of the trench from being closed off prior to the trench being completely filled. After a masking layer is deposited and patterned, the trench is etched and then the masking layer is removed. A first liner insulating layer is grown or deposited and is then etched anisotropically to remove the layer from the top surface of the substrate as well as from the top portion of the walls of the trench. A second, thinner liner layer is grown or deposited on the exposed portion of the walls of the trench to provide surface and edge protection. A polysilicon layer is then deposited to fill the trench and is planarized to remove the portion deposited on the top surface of the substrate. Alternatively, the thinner oxide liner can be omitted, and the polysilicon is removed by chemical mechanical polishing until the trench liner oxide appears on the top surface. An overlaying insulation layer is then deposited. A passivation layer may be subsequently deposited on the bottom surface. The process is particularly suited for etching and filling steps that leave a re-entrant profile at the top of the trench. The trench structure may provide dielectric isolation for the cells of a photovoltaic generator. An MOS-gated device may be integrated into the same chip and may be a lateral or vertical MOSFET or a lateral or vertical IGBT.

Claims

1. A process for fabricating a trench structure of a semiconductor device, said process comprising the steps of:

forming a masking layer on a top surface of a silicon substrate;

patterning and etching away selected regions of said masking layer to form a plurality of spaced openings therein;

etching away portions of said silicon substrate which are located beneath said plural openings in said masking layer to form a trench in said silicon substrate;

removing said masking layer;

forming a first liner insulation layer on the interior walls and bottom surface of said trench and on said top surface of said silicon substrate;

etching away a portion of said first liner insulation layer that is atop said silicon substrate and that covers an upper portion of the interior walls of said trench, thereby removing any re-entrant structure in said upper portion of said first insulation layer and in said interior walls of said trench that is located at an entrance to said trench;

depositing a layer of polysilicon on said top surface of said substrate and in said trench such that said trench is filled; and

removing a portion of said polysilicon layer that is formed atop said top surface of said substrate.

2. The process of claim 1 further comprising the step of depositing an overlaying insulation layer on said top surface of said silicon substrate after said portion of said polysilicon layer is removed.

3. The process of claim 1 further comprising the step of removing a portion of a bottom surface of said silicon substrate at least until the bottom surface of said trench is reached.

4. The process of claim 3 wherein a further portion of said bottom surface of said silicon substrate is removed at least until the portion of said first liner insulation layer which lines said sidewall surface of said trench is exposed.

5. The process of claim 3 further comprising the step of coating said top surface of said substrate with a protective coating prior to said step of removing a portion of said bottom surface of said silicon substrate.

6. The process of claim 4 further comprising the step of depositing a passivation layer on said bottom surface of said substrate.

7. The process of claim 6 wherein said passivation layer is comprised of silicon dioxide.

8. The process of claim 1 wherein said masking layer is comprised of one of the following:

photoresist, TEOS and silicon dioxide.

9. The process of claim 1 wherein said first liner insulation layer is comprised of silicon dioxide.

10. The process of claim 1 wherein said first liner insulation layer is comprised of TEOS.

11. The process of claim 1 further comprising the step of forming a second liner insulation layer, which has a thickness less than that of said first liner insulation layer, on the exposed portion of the interior walls of said trench and on said top surface of said silicon substrate prior to depositing said layer of polysilicon.

12. The process of claim 11 wherein said second liner insulation layer is comprised of one of silicon dioxide and TEOS.

13. The process of claim 1 wherein said silicon substrate is of one conductivity type, and said process further comprises the steps of:

introducing impurities of another conductivity type, which is of opposite conductivity type to said one conductivity type, into selected regions of a top surface of said silicon substrate to form first diffused regions; and

introducing impurities of said one conductivity type into further selected regions of said top surface of said silicon substrate to form second diffused regions which are spaced from and which surround said first diffused regions prior to forming said masking layer.

14. The process of claim 2 further comprising the step of patterning and etching away selected portions of said overlaying insulation layer to form an opening to said first diffused region and an opening to said second diffused regions in each of said cells.

15. The process of claim 14 further comprising the steps of depositing a conductive layer;

and

patterning and etching away portions of said conductive layer to form at least one interconnecting contact which contacts a respective first diffused region of one of said cells and a second diffused region of an adjoining one of said cells.

16. The process of claim 15 further comprising the step of removing a portion of a bottom surface of said silicon substrate at least until the bottom surface of said trench is reached.

17. A process of forming a trench in a silicon wafer;

said process comprising the steps of etching at least one opening into the surface of said wafer;

said opening having a pair of spaced walls and a bottom surface at a given depth;

forming an insulator layer on the walls and bottom surface of said opening and on a portion of the surface of said wafer that is adjacent to said walls of said opening;

selectively removing a portion of said insulation layer from said surface of said wafer and from an upper region of said walls of said opening, whereby any material of said insulation layer that has a re-entrantly thickened profile at the entrance to said opening is removed;

depositing polysilicon on said top surface of said substrate and in said trench so that said trench is filled; and

removing a portion of said polysilicon layer that is formed atop said top surface of said substrate.

18. The process of claim 17 further comprising the step of forming a second insulation layer on the walls and said bottom surface of said opening and on said portion of said surface of said wafer adjacent to said walls of said opening;

and selectively removing a portion of said second insulation layer from said surface of said wafer and from the upper region of said walls of said opening prior to depositing said layer of polysilicon, whereby any material of said insulation layer that has a re-entrantly thickened profile at the entrance to said opening is removed prior to depositing said layer of polysilicon.

19. The process of claim 17 wherein said step of depositing a dielectric material comprises forming subsequent insulator layers on the walls and the bottom surface of said opening and on the surface of said wafer adjacent to said walls until said opening is filled.

20. The process of claim 18 wherein said step of depositing a dielectric material comprises forming subsequent insulator layers on the walls and the bottom surface of said opening and on the surface of said wafer adjacent to said walls until said trench is filled.

21. The process of claim 17 wherein said first insulation layer is comprised of one of silicon dioxide and TEOS.

22. The process of claim 18 wherein said second insulation layer is comprised of one of silicon dioxide and TEOS.

23. The process of claim 19 wherein said subsequent insulation layers are comprised of TEOS.

24. The process of claim 20 wherein said subsequent insulation layers are comprised of TEOS.