Semiconductor device

• US 6,054,730 A
• Filed: 01/05/1998
• Issued: 04/25/2000
• Est. Priority Date: 01/08/1997
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Noguchi, Mitsuhiro
• Primary Examiner(s): Munson, Gene M.
• Application Number:
  US09/003,494
• Time in Patent Office: 841 Days
• Field of Search: 257/306, 257/310
• US Class Current: 257/306
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/05 Making the transistor
• CPC Class Codes: H10B 12/30 DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
• CPC Class Codes: H10B 12/31 having a storage electrode stacked over the transistor

Abstract

A semiconductor device comprises a transistor having a gate, a source, and a drain, one of the source and drain being a first end, and the other being a second end, and a capacitor comprising a storage node connected to the first end and a plate electrode, wherein a current flowing between the source and drain when a potential Va is applied to the second end and a potential Vb, which is lower than Va, is applied to the storage node is smaller than a current flowing the source and the drain when a potential Vb is applied to the second end and a potential Va is applied to the storage node, while the potential of the gate and the potential of the plate electrode are maintained to be constant. Here, the transistor should preferably be a MIS-type.

Claims

1. A semiconductor device comprising:

a transistor having a gate, a source, and a drain, one of the source and drain being a first end and the other being a second end; and

a capacitor comprising a storage node connected to the first end, and a plate electrode, wherein

a first current flowing between the source and drain when a potential Va is applied to said second end and a potential Vb, which is higher than Va, is applied to said storage node is smaller than a second current flowing between the source and drain when a potential Vb is applied to said second end and a potential Va is applied to said storage node, while a potential of the gate and a potential of the plate electrode are maintained to be constant and a voltage of the gate is smaller than a threshold voltage.

2. A semiconductor device comprising:

a transistor having a gate connected to a gate control line, a source, and a drain, one of the source and drain being a first main electrode connected to a data transfer line, and the other being a second main electrode; and

a capacitor comprising a storage node connected to the second main electrode, and a plate electrode connected to a common electrode, wherein

the transistor and the capacitor constitute a memory cell, and

a threshold voltage when a potential Va is applied to said data transfer line and a potential Vb, which is higher than Va, is applied to said storage node is higher than a threshold voltage when a potential Vb is applied to said data transfer line and a potential Va is applied to said storage node, while the potential of the gate and a potential of the plate electrode are maintained to be constant.

3. A semiconductor device according to claim 2, wherein a current flowing between the source and drain is larger than a current flowing between the second main electrode and a substrate, when a voltage of the gate is smaller than a threshold voltage.

4. A semiconductor device according to claim 2, wherein a plurality of memory cells are connected to one data transfer line, and the data transfer line has a capacitance larger than the storage node has.

5. A semiconductor device according to claim 2, wherein an impurity density of a channel region in a side of the first main electrode is higher than in a side of the second main electrode, below the gate electrode.

6. A semiconductor device according to claim 5, wherein the channel region having the higher impurity density is formed by a mask different from a mask for forming the source or drain.

7. A semiconductor device according to claim 5, wherein the channel region having the higher impurity density is formed apart from an interface between the gate insulating film and the substrate.

8. A semiconductor device according to claim 2, wherein the transistor is a transistor having a threshold voltage which decreases as a channel width is narrowed, and the channel width is wider in a side of the first main electrode than in a side of the second main electrode.

9. A semiconductor device according to claim 2, wherein

the transistor is a transistor having a threshold voltage which increases as a channel width is narrowed,

the gate is substantially formed on a substrate main surface along a first direction,

among first and second cross-sectional views parallel to each other below the gate electrode in the first direction, the first cross-section is closer to the first main electrode of the transistor than the second cross-section,

a distance from the first cross-section to an end of the gate is equal to a distance from the second cross-section to the other end of the gate, and

a width of a transistor region having a contact with the gate through a gate insulating film along the substrate main surface on the first cross-section is narrower than a width of a transistor region having a contact with the gate through a gate insulating film along the substrate main surface on the second cross-section.

10. A semiconductor device according to claim 9, wherein the width of the transistor region on arbitrary one of the first cross-sections is narrower than the width of transistor region on arbitrary one of the second cross-sections.

11. A semiconductor device according to claim 2, wherein

the transistor is a transistor having a threshold voltage which decreases as a channel width is narrowed,

the gate is formed on a substrate main surface along a first direction,

among first and second cross-sectional views parallel to each other below the gate electrode in the first direction, the first cross-section is closer to the first main electrode of the transistor than the second cross-section,

a distance from the first cross-section to an end of the gate is equal to a distance from the second cross-section to the other end of the gate, and

a width of a transistor region having a contact with the gate through a gate insulating film along the substrate main surface on the first cross-section is wider than a width of a transistor region having a contact with the gate through a gate insulating film along the substrate main surface on the second cross-section.

12. A semiconductor device according to claim 11, wherein the width of the transistor region on arbitrary one of the first cross-sections is wider than the width of transistor region on arbitrary one of the second cross-sections.

13. A semiconductor device according to claim 2, wherein

the memory cell is formed on a semiconductor substrate,

an element isolation insulating film is embedded in a peripheral region of the transistor, and

an angle between the main surface of said semiconductor substrate and a side surface of the transistor region across said element isolation insulating film is greater at a side of the second main electrode than at a side of the first main electrode, in a channel width direction of the transistor.

14. A semiconductor device according to claim 2, wherein

the transistor is formed along a substrate main surface, such that a side surface of the transistor is in contact with an element isolation insulating film,

the gate electrode is formed on a substrate main surface along a first direction,

among first and second cross-sectional views parallel to each other below the gate electrode in the first direction, the first cross-section is closer to the first main electrode of the transistor than the second cross-section,

a distance from the first cross-section to an end of the gate electrode is equal to a distance from the second cross-section to the other end of the gate electrode, and

an angle forming between the main surface of said semiconductor substrate and a side surface of the transistor region on the first cross-section across said element isolation insulating film is smaller than an angle forming between the main surface of said semiconductor substrate a side surface of the transistor region on the second cross-section across said element isolation insulating film.

15. A semiconductor device according to claim 2, wherein

the capacitor includes a second transistor having a source a drain and a gate connected to the second main electrode to function as a storage node,

a substrate electrode of the second transistor or at least one of the source and drain thereof is connected to a common electrode to form a capacitor between said second main electrode and the common electrode, and

a threshold voltage of the second transistor is between a minimum voltage of the storage node and a maximum voltage of the storage node.

16. A semiconductor device according to claim 2, wherein

the gate is formed on a substrate main surface along a first direction,

among first and second cross-sectional views parallel to each other below the gate electrode in the first direction, the first cross-section is closer to the first main electrode of the transistor than the second cross-section,

a distance from the first cross-section to an end of the gate is equal to a distance from the second cross-section to the other end of the gate, and

in a direction normal to the substrate main surface, a distance of the gate insulating film from an end of a depletion layer in the substrate on the second cross-section is greater than a distance on the first cross-section, on condition that a potential difference between the source and drain is 0 V, and that a voltage of the gate is smaller than the threshold voltage.

17. A semiconductor device according to claim 2, wherein

the transistor region is formed along a substrate main surface so as to have a side surface in contact with an element isolation insulating film,

the gate is formed on a substrate main surface along a first direction,

among first and second cross-sectional views parallel to each other below the gate electrode in the first direction, the first cross-section is closer to the first main electrode of the transistor than the second cross-section,

a distance from the first cross-section to an end of the gate electrode is equal to a distance from the second cross-section to the other end of the gate electrode, and

a height from an interface between the element isolation insulating film and the gate electrode to a an interface between the gate-insulating film and the substrate main surface around the side surface of the transistor region on the second cross-section is smaller than a height from an interface between the element isolation insulating film and the gate electrode to an interface between the gate-insulating film and the substrate main surface around the side surface of the transistor region on the first cross-section.

21. A semiconductor device according to claim 2, wherein

the transistor region is formed along a substrate main surface so as to have a side surface in contact with an element isolation insulating film,

the gate is formed along a first direction,

among first and second cross-sectional views parallel to each other below the gate electrode in the first direction, the first cross-section is closer to the first main electrode of the transistor than the second cross-section,

a distance from the first cross-section to an end of the gate electrode is equal to a distance from the second cross-section to the other end of the gate electrode, and

a radius of curvature of a corner portion comprising the semiconductor region formed by a side surface of the transistor region and by an interface between the semiconductor region and a gate insulating film on the first cross-section, is greater than a radius of curvature of a corner portion on the second cross-section.

18. A semiconductor comprising:

a transistor having a gate, a source, and a drain, one of the source and drain being a first main electrode and the other being a second main electrode connected to the gate electrode; and

a capacitor comprising a storage node connected to the second main electrode, and a plate electrode, wherein

a predetermined voltage is applied to the plate electrode such that the storage node has potentials of two values, one being a first voltage higher than a threshold voltage of the transistor and the other being a second voltage lower than the threshold voltage,

the storage node has a higher potential than the first main electrode when the storage node is applied with the first voltage, and the first main electrode has a higher potential than the storage node when the storage node is applied with the second voltage, and

the transistor has a lower threshold voltage when the storage node is applied with the first voltage than when the storage node is applied with the second voltage.

19. A semiconductor device comprising:

a transistor having a gate connected to a gate control line, a source, and a drain, one of the source and drain being a first main electrode connected to a data transfer line, and the other being a second main electrode; and

a capacitor having a storage node connected to the second main electrode and a plate electrode connected to a common electrode, wherein

the transistor and the capacitor constitute a memory cell,

the storage node is electrically connected with alternatively two voltage sources having different voltages from each other via said the data transfer line and said transistor, and data are stored as information of an electric charge or an electric polarity, and

a retention time of an electric charge or an electric polarity is longer when data holding state is set after the storage node is connected to the first voltage source having a high voltage than when data holding state is set after the storage node is connected to the second voltage source having a low voltage.

20. A semiconductor device according to claim 19, wherein

the data transfer line is connected to a plurality of memory cells,

after said data transfer line is connected to the first voltage source and the gate voltage is set at the third predetermined voltage higher than the threshold voltage, then the first data retention time of the memory cell is determined on condition, that the memory cell is connected to the second voltage after changing the gate voltage to the fourth predetermined voltage lower than the threshold voltage, and

after said data transfer line is connected to the second voltage source and the gate voltage is set at the third predetermined voltage, and then the second data retention time of the memory cell is determined on condition that the memory cell is connected to the first voltage after changing the gate voltage to the fourth predetermined voltage, and

the first data retention time is longer than the second data retention time.