Inductor formed at least partially in a substrate

• US 6,054,750 A
• Filed: 02/27/1998
• Issued: 04/25/2000
• Est. Priority Date: 12/22/1995
• Status: Expired due to Term

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Imam, Mohamed A., Yoganathan, Sittampalam
• Primary Examiner(s): WOJCIECHOWICZ, EDWARD JOSEPH
• Application Number:
  US09/032,430
• Time in Patent Office: 788 Days
• Field of Search: 257/531, 257/281, 257/379, 257/401
• US Class Current: 257/531
• CPC Class Codes: H01L 2223/6611 Wire connections
• CPC Class Codes: H01L 2224/4813 Connecting within a semiconductor or solid-state body, i.e. fly wire, bridge wire
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/08 including only semiconductor components of a single kind
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/19104 on the semiconductor or solid-state device, i.e. passive-on-chip

Abstract

A method of making an inductor and the inductor. The inductor comprises a plurality of serially connected transistors at least partially formed in a substrate, preferably a silicon on insulator substrate, and comprises a gate common to the plurality of transistors. The plurality of transistors, transistor contacts, and electrical interconnects form the coil of the inductor and the gate common to the plurality of transistors forms the core of the inductor. Two inductors of the invention are magnetically coupled to form a transformer of the invention. A control transistor is serially connected to the primary inductor of the transformer. The control transistor is gated by a periodic output signal of a ring oscillator. An actuation and a deactuation of the control transistor allows the current in the primary coil to vary creating a changing magnetic flux in the primary and secondary cores and inducing a fluctuating current in the secondary coil.

Claims

1. An inductor formed at least partially in a semiconductor base layer, the inductor comprising:

a core fabricated from a gate, said core having a length and operably coupled to the base layer; and

a coil comprising a plurality of alternating serially connected active areas and metal connections, said coil partially formed within an active area of said base layer and traversing at least a portion of the length of the core.

2. The inductor as specified in claim 1, wherein said coil comprises a conduction path formed by a plurality of transistors.

3. The inductor as specified in claim 2, wherein each of said transistors comprises a channel formed in said active of said base layer.

4. The inductor as specified in claim 2, wherein said core is a transistor gate common to said plurality of transistors.

5. The inductor as specified in claim 4, wherein said transistor gate overlies the base layer.

6. An inductor, comprising:

at least one transistor having a gate, source and drain fabricated on a semiconductor substrate;

a coil including the source, the drain, and a conductor, the conductor coupled to the source and drain; and

a core operably coupled to the gate, wherein said coil extends around said core.

7. The inductor as specified in claim 6, wherein said coil comprises a conduction path formed by a plurality of serially connected transistors having said core as a common gate.

8. The inductor as specified in claim 7, wherein a portion of each transistor of said plurality of serially connected transistors is formed in an active area of substrate.

9. An inductor having a core and a coil traversing the core, comprising:

a plurality of serially connected transistors, each transistor having a source and drain region, wherein the source of one transistor is operably coupled by a conductive material to the drain of another transistor; and

a transistor gate, said plurality of serially connected transistors sharing said transistor gate, wherein the core comprises said gate, and wherein the coil comprises a conduction path comprising a channel region of each of said transistors of said plurality of serially connected transistors in series with the conductive material.

10. The inductor as specified in claim 9, wherein the conduction path in each transistor of said plurality of serially connected transistors is formed in an active area of a semiconductor device substrate.

11. The inductor as specified in claim 9, further comprising a plurality of interconnects, each of said interconnects connecting a source and a drain of two serially connected transistors of said plurality of serially connected transistors, said interconnects extending on the opposite side of said gate from said channel regions.

12. The inductor as specified in claim 11, wherein the coil comprises said plurality of interconnects.

13. A semiconductor structure, comprising:

a silicon on insulator substrate having a transistor formed therein;

a polysilicon layer overlying the silicon on insulator substrate, said polysilicon layer electrically isolated from said substrate, said polysilicon layer configured to function as a gate of said transistor and an inductor core;

a plurality of serially connected transistors sharing said transistor gate; and

a conduction path formed from said plurality of serially connected transistors formed in an active area of the silicon on insulator substrate wherein the conduction path encircles the inductor core.

14. The structure as specified in claim 13, wherein said plurality of serially connected transistors function as an inductor coil formed underlying the polysilicon layer.

15. An inductor structure formed using a silicon on insulator substrate, the inductor structure comprising:

a) a plurality of alternating serially connected active regions formed in said silicon on insulator substrate and conductive segments above said silicon on insulator substrate; and

b) a plurality of electrically insulative regions, each of said electrically insulative regions electrically operably coupled together isolating said active regions from each other.

16. The structure as specified in claim 15, further comprising a plurality of electrical interconnects serially connecting the plurality of active regions, wherein said plurality of electrical interconnects form a further portion of said inductor coil.

17. The structure as specified in claim 16, further comprising a gate overlying said plurality of active regions, wherein said gate and said active regions form a plurality of transistors, and wherein said gate is an inductor core encompassed by said inductor coil.

18. A method of inducing current flow comprising:

actuating a plurality of transistors, each transistor utilizing a gate portion and hav active area formed in a substrate wherein the gate portions of transistors are connected together;

conducting current in a path encircling said gate portions in response to said step of actuating, said path comprising said active areas serially connected to each other;

creating magnetic lines of flux in said gate portions and in a plurality of further active areas in response to conducting current in the path; and

inducing current flow in said plurality of further active areas in response to creating magnetic lines of flux.

19. A memory system comprising:

a monolithic memory device comprising;

a plurality of transistors each transistor having an active region and a gate region wherein the active regions of the plurality of transistors are serially connected to one another by a conduction path;

a transistor gate operably coupled to the gate regions, wherein said transistor gate functions as an inductor core, and the conduction path functions as a portion of an inductor coil and the conduction path in series with the active regions of the plurality of transistors encircles the inductor core; and

a processor configured to access said monolithic memory device.

20. A transformer, comprising:

a plurality of serially connected transistors at least partially formed in a base layer, each transistor having a source and a drain and a channel region, wherein the source of one transistor is serially connected by a conductive segment located above the base layer to the drain of a subsequent transistor, said plurality of serially connected transistors forming a coil of a first inductor of the transformer;

a gate overlying the channel region of each of said transistors and within the coil, said gate forming a core of the first inductor; and

a second inductor at least partially formed in the base layer, the second inductor is parallel to the first inductor and magnetically coupled to the first inductor.

21. The transformer as specified in claim 20, wherein said gate is a core of said second inductor.

22. A transformer, comprising:

a) a first plurality of serially connected transistors each having a source and a drain, wherein the source of one transistor is serially connected by a conductive segment to the drain of a next transistor, said first plurality of serially connected transistors forming a coil of a first inductor of the transformer;

b) a first gate overlying and openly coupled to a channel region of each of said transistors of said first plurality of serially connected transistors, said first gate forming a core of the first inductor wherein said core of the first inductor is within the coil of the first inductor;

c) a second plurality of serially connected transistors each having a source and a drain, wherein the source of one of the transistors is serially connected by a conductive segment to the drain of the next of the transistors, said second plurality of serially connected transistors forming a coil of a second inductor of the transformer; and

d) a second gate overlying and operably coupled to a channel region of each of said transistors of said second plurality of serially connected transistors, said second gate forming a core of the second inductor within the coil of the second inductor coil of, wherein said first and said second inductors are magnetically coupled to each other.

23. The transformer as specified in claim 22, wherein said first and said second gates are physically connected.

24. The transformer as specified in claim 22, further comprising a circuit in electrical communication with said second inductor, said circuit configured to convert the potential of the secondary inductor to a constant DC potential.

25. The transformer as specified in claim 24, further comprising a control circuit configured to supply a fluctuating potential to said first inductor.

26. The transformer as specified in claim 25, further comprising an oscillator circuit configured to control said control circuit.

27. An inductor partially formed in a semiconductor base layer, the inductor comprising:

a core having a rectangular cross-section; and

a coil formed partially in an active area of said base layer, said coil comprising serially connected source, drain, and channel regions of a plurality of transistors of which said core is coupled to the channel regions of the plurality of transistors to form a gate, and each of the plurality of transistors is interconnected by a conductive segment above the semiconductor base layer.

28. An inductor, comprising:

a first core comprising a first transistor gate;

a first coil comprising a first transistor channel region, wherein a first conductive element is operably coupled to the transistor channel region forming a loop around said first core;

a core comprising a transistor gate, said core electrically coupled to the first core; and

a coil comprising a transistor channel region, wherein a conductive element is operably coupled to the transistor channel region forming a loop around said core, and the coil is electrically coupled to the first coil.

29. An inductor structure formed using a silicon on insulator substrate, comprising:

a plurality of active regions formed in said silicon on insulator substrate;

a plurality of electrically insulative regions, each of said electrically insulative regions electrically isolating said active regions from each other;

a plurality of electrical interconnects located above the silicon on insulator substrate and serially connecting the plurality of active regions such that one active region is serially connected to a subsequent active region, wherein said plurality of electrical interconnects and said plurality of active regions form an inductor coil; and

a gate overlying said plurality of active regions, wherein said gate and said active regions and, coupling the electrically insulative regions to each other form a plurality of transistors, and wherein said gate forms an inductor core encompassed by said inductor coil.

30. An inductor formed at least partially in a semiconductor base layer, the inductor comprising:

a core fabricated from a gate, the core having a length and operably coupled to the base layer;

a coil, the coil partially formed within a plurality of active areas of the base layer and traversing at least a portion of the length of the core and the coil partially formed by a plurality of metal connections serially coupling the plurality of active areas.

31. The inductor of claim 30, wherein the core is electrically insulated from the base area.

32. The inductor of claim 31, wherein a portion of the core is separated from a semiconductor substrate by at least three insulating layers.

33. An inductor comprising:

at least one transistor having a gate, source and drain fabricated on a semiconductor substrate having an oxide layer;

a coil including the source, the drain, and a conductor, the conductor coupled to the source and drain; and

a core operably coupled to the gate, wherein the coil extends around the core and the coil and the core are above the oxide layer.

34. The inductor of claim 33, wherein the one transistor is formed by a complementary metal-oxide semiconductor process.

35. The inductor of claim 33, wherein the core is electrically insulated from the gate.

36. An inductor having a core and a coil traversing the core, the inductor comprising:

a plurality of serially connected transistors, each transistor having a source and drain region surrounded by an insulative material, wherein the source of one transistor is operably coupled by a conductive material to the drain of another transistor; and

a transistor gate, the plurality of serially connected transistors sharing the transistor gate, wherein the core comprises the gate, and wherein the coil comprises a conduction path comprising a channel region of each of the transistors of the plurality of serially connected transistors in series with the conductive material.

37. The inductor of claim 36, wherein the plurality of serially connected transistors is a field-effect transistor.

38. The inductor of claim 36, wherein the transistor gate is fabricated from a single layer of polysilicon.

39. A semiconductor structure, comprising:

a silicon on insulator substrate having a transistor formed therein;

a polysilicon layer overlying the silicon on insulator substrate, the polysilicon layer electrically isolated from the substrate, the polysilicon layer configured to function as a gate of the transistor and an inductor core;

a plurality of serially connected transistors sharing the transistor gate; and

a conduction path formed from the plurality of serially connected transistors formed in an active area of the silicon on insulator substrate wherein the conduction path encircles the inductor core at least twice.

40. The semiconductor structure of claim 39, wherein the silicon on insulator substrate is a p-type semiconductor.

41. The semiconductor structure of claim 39, wherein the polysilicon layer has a rectangular cross-section.

42. An inductor partially formed in a semiconductor base layer, the inductor comprising:

a core having a rectangular cross-section located above an oxide layer; and

a coil formed partially in an active area of the base layer, the active area surrounded by an insulative region, and the coil comprising serially connected source, drain, and channel regions of a plurality of transistors, wherein the core is coupled to the channel regions of the plurality of transistors to form a gate.

43. The inductor of claim 42, wherein the core has a rectangular top surface.

44. The inductor of claim 42, wherein the coil has a length and a conductivity and the conductivity varies along the length of the coil.

45. An inductor, comprising:

a first conductive core comprising a first metal-oxide semiconductor (MOS) transistor gate;

a first coil comprising a first MOS transistor channel region, wherein a first conductive element is operably coupled to the MOS transistor channel region forming a loop around the first core;

a conductive core comprising a MOS transistor gate, the conductive core electrically coupled to the first conductive core; and

a coil comprising a MOS transistor channel region, wherein a conductive element is operably coupled to the MOS transistor channel region forming a loop around the conductive, and the coil is electrically coupled to the first coil.

46. The inductor of claim 45, wherein the first conductive core is fabricated from polysilicon.

47. The inductor of claim 46, wherein the conductive core is fabricated from a metal.

48. An inductor structure formed using a silicon on insulator substrate, comprising:

a plurality of active regions formed in an and above an oxide of the silicon on insulator substrate;

a plurality of electrically insulative regions, each of the plurality of electrically insulative regions electrically isolating the active regions from each other;

a plurality of electrical interconnects located above the silicon on insulator substrate and serially connecting the plurality of active regions such that one active region is serially connected to a subsequent active region, wherein the plurality of electrical interconnects and the plurality of active regions form an inductor coil above an insulator; and

a gate overlying the plurality of active regions, wherein the gate forms an inductor core encompassed by the inductor coil.

49. The inductor structure of claim 48, wherein each of the plurality of active regions includes a drain, a source, and a channel.