Semiconductor apparatus, circuit board and combination thereof

• US 6,054,757 A
• Filed: 02/26/1998
• Issued: 04/25/2000
• Est. Priority Date: 02/27/1997
• Status: Expired due to Fees

• Current Assignee: Oki Semiconductor Company Limited (ROHM Co., Ltd.)
• Original Assignee: OKI Electric Industry Company Limited
• Inventors: Kobayashi, Harufumi
• Primary Examiner(s): Whitehead, Jr., Carl
• Assistant Examiner(s): POTTER, ROY KARL
• Application Number:
  US09/030,924
• Time in Patent Office: 789 Days
• Field of Search: 257/787, 257/778, 257/690, 257/730, 257/692, 257/737, 257/738
• US Class Current: 257/690
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/32 Holders for supporting the complete device in operation, i.e. detachable fixtures H01L23/40 takes precedence
• CPC Class Codes: H01L 23/49555 the bent parts being the outer leads
• CPC Class Codes: H01L 23/49805 the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H05K 1/141 One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters H05K1/142 and H05K1/147 take precedence
• CPC Class Codes: H05K 1/145 Arrangements wherein electric components are disposed between and simultaneously connected to two planar printed circuit boards, e.g. Cordwood modules
• CPC Class Codes: H05K 1/183 Components mounted in and supported by recessed areas of the printed circuit board
• CPC Class Codes: H05K 2201/049 PCB for one component, e.g. for mounting onto mother PCB
• CPC Class Codes: H05K 2201/10689 Leaded Integrated Circuit [IC] package, e.g. dual-in-line [DIL]
• CPC Class Codes: H05K 2201/10734 Ball grid array [BGA]; Bump grid array

Abstract

A semiconductor apparatus includes a semiconductor chip contained in a package; a first set of connection terminals, of which one ends are connected to the semiconductor chip and the other ends are connected onto a first connection plane outside of the package; and a second set of connection terminals, of which one ends are connected to the semiconductor chip and the other ends are connected onto a second connection plane outside of the package. The first and second connection planes are electrically connected to a circuit board.

Claims

1. A semiconductor apparatus, comprising:

a semiconductor chip contained in a package;

a first set of connection terminals, each of the connection terminals of the first set having one end connected to the semiconductor chip, and another end connected onto a first connection plane outside of the package; and

a second set of connection terminals, each of the connection terminals of the second set having one end connected to the semiconductor chip, and another end connected onto a second connection plane outside of the package, wherein

the first and second connection planes are electrically connected to a circuit board; and

the first and second sets of connection terminals are arranged alternately with a predetermined pitch in the package.

2. The semiconductor apparatus, according to claim 1, wherein:

the first set of connection terminals are arranged on a first surface of the package, while the second set of connection terminals are arranged on a second surface of the package.

3. The semiconductor apparatus, according to claim 2, wherein

the first and second surfaces are perpendicular to each other.

4. The semiconductor apparatus, according to claim 3:

wherein the package includes an insulation substrate, wherein

the first set of connection terminals are arranged at a bottom surface of the insulation substrate, while the second set of connection terminals are arranged at a side surface of the insulation substrate.

5. The semiconductor apparatus, according to claim 4, wherein

the semiconductor apparatus is of BGA (Ball Grid Array) type.

6. The semiconductor apparatus, according to claim 5, wherein

the first set of connection terminals are connected to first contact pins,

the second set of connection terminals are connected to second contact pins, and

the first and second contact pins extend in the same direction to be connected to the circuit board.

7. The semiconductor apparatus, according to claim 6, wherein

the semiconductor apparatus is covered with a protection socket.

8. The semiconductor apparatus, according to claim 1, wherein

the first and second sets of connection terminals are arranged on a common surface, and extend in different directions from each other.

9. The semiconductor apparatus, according to claim 8, wherein

the first and second connection planes are arranged perpendicularly to each other, and

the first set of connection terminals extend to the first connection plane, while the second set of connection terminals extend to the second connection plane.

10. The semiconductor apparatus, according to claim 8, wherein

the first and second connection planes are arranged parallel to each other at different levels, and

the first set of connection terminals extend to the first connection plane, and the second set of connection terminals extend parallel to the second connection plane.

11. A combination of a semiconductor apparatus and a circuit board, wherein,

the semiconductor apparatus comprises:

(1) a semiconductor chip contained in a package;

(2) a first set of connection terminals, each of the connection terminals of the first set having one end connected to the semiconductor chip; and

(3) a second set of connection terminals, each of the connection terminals of the second set having one end connected to the semiconductor chip, wherein the first and second sets of connection terminals are arranged alternately with a predetermined pitch, and the circuit board comprises;

(1) a first connection plane onto which other ends of the first set of connection terminals are connected; and

(2) a second connection plane onto which other ends of the second set of connection terminals are connected.

12. The combination, according to claim 11, wherein

the first and second sets of connection terminals of the semiconductor apparatus are respectively arranged on first and second surfaces of the package, which are perpendicular to each other.

13. The combination, according to claim 12, wherein

the package of the semiconductor apparatus further comprises an insulation substrate, of which a bottom surface and a side surface are arranged respectively parallel to the first and second connection planes of the circuit board, and

the first and second sets of connection terminals are positioned on the bottom surface and side surface of the insulation substrate, respectively.

14. The combination, according to claim 11, wherein

the first and second sets of connection terminals of the semiconductor apparatus are arranged on a common surface of the package, and extend in different directions.

15. The combination, according to claim 14, wherein

the first and second connection planes of the circuit board are arranged perpendicularly to each other, and

the first set of connection terminals extend to the first connection plane, while the second set of connection terminals extend to the second connection plane.

16. The combination, according to claim 14, wherein

the first and second connection planes of the circuit board are arranged parallel to each other a different levels, and

the first set of connection terminals extend to the first connection plane, and the second set of connection terminals extend parallel to the second connection plane.

17. A semiconductor apparatus, comprising:

a semiconductor chip contained in a package;

a first set of connection terminals, each of the connection terminals of the first set having one end connected to the semiconductor chip, and another end connected onto a first connection plane outside of the package; and

a second set of connection terminals, each of the connection terminals of the second set having one end connected to the semiconductor chip, and another end connected onto a second connection plane outside of the package, wherein

the first and second sets of connection terminals are arranged alternately with a predetermined pitch in the package;

and wherein the first set of connection terminals are connected to first contact pins,

the second set of connection terminals are connected to second contact pins, and

the first and second contact pins extend in the same direction to be connected to the circuit board.