Thin type semiconductor package

• US 6,054,774 A
• Filed: 07/09/1997
• Issued: 04/25/2000
• Est. Priority Date: 03/22/1994
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Iwasaki, Hiroshi, Ohmori, Jun
• Primary Examiner(s): Hardy, David B.
• Application Number:
  US08/890,633
• Time in Patent Office: 1,021 Days
• Field of Search: 257/679, 257/690, 257/691, 257/692, 257/773, 257/786, 257/777, 257/778, 257/780, 235/488, 235/492
• US Class Current: 257/786
• CPC Class Codes: G06K 19/07743 External electrical contacts
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 23/49855 for flat-cards, e.g. credit cards cards per se G06K19/00
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01039 Yttrium [Y]
• CPC Class Codes: H01L 2924/01057 Lanthanum [La]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/12041 LED
• CPC Class Codes: H01L 2924/15153 the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/15165 Monolayer substrate
• CPC Class Codes: H01L 2924/181 Encapsulation
• CPC Class Codes: H01L 2924/18161 of a flip chip

Abstract

A semiconductor package having a board, at least one semiconductor chip, and flat type external connecting terminals, the board having a wiring circuit including connecting portions on a first main surface, the semiconductor being mounted on the first main surface, the flat type external connecting terminals being electrically connected to the semiconductor chip and formed on a second main surface of the board, wherein the flat type external connecting terminals are disposed in such a manner that any straight line which is arbitrarily drawn across the surface of a region to form the flat type external connecting terminals of the board runs on at least one of the flat type external connecting terminals.

Claims

1. A semiconductor package comprising:

a board having oppositely facing first and second main surfaces and a wiring circuit including connecting portions on the first main surface;

at least one semiconductor chip mounted on the first main surface of the board; and

flat type external connecting terminals on the second main surface of the board and electrically connected to the semiconductor chip through the connecting portions of the wiring circuit, the flat type external connecting terminals each having an area size, being asymmetrically disposed on the second main surface of the board, and being spaced by a curved separating portion extending substantially across the second main surface, the area size, asymmetric disposition, and spacing of the flat type external connecting terminals being related so that all straight lines in a region containing the flat type external connecting terminals cross at least one flat type external connecting terminal, thereby to strengthen the board against bending.

2. The semiconductor package of claim 1, wherein the curved separating portion is of generally S-shaped configuration.

3. The semiconductor package of claim 1 including at least two of said curved separating portions on opposite sides on at least one of the flat type external connecting terminals extending substantially across the second main surface.

4. The semiconductor package of claim 1 including at least three of said curved separating portions, one of said curved separating portions lying between at least two of the flat type external connecting terminals extending substantially across the second main surface, and the other two of the at least three curved separating portions lying on opposite sides of the at least two of the flat type external connecting terminals extending substantially across the second main surface.

5. The semiconductor package of claim 1 including a resin layer filling a space between the semiconductor chip surface and the first main surface of the board.

6. The semiconductor package of claim 1, wherein said first main surface is recessed in the board to provide a relatively thick peripheral margin, the connecting portions of the wiring circuit being located in said peripheral margin, and including bonding wires connecting the semiconductor chip to the connecting portions.

7. The semiconductor package of claim 6 including a resin layer filling the recessed first main surface and encapsulating at least part of the semiconductor chip and the bonding wires.

8. The semiconductor package of claim 1, wherein the connecting portions of the wiring circuit are located in a peripheral margin of the board around the semiconductor chip, and including bonding wires connecting the semiconductor chip to the connecting portions.

9. The semiconductor package of claim 8 including a resin layer encapsulating at least part of the semiconductor chip and the bonding wires.

10. The semiconductor package of claim 1, wherein the semiconductor chip includes terminal bumps for connection to the connecting portions and including a resin layer filling a space between the semiconductor chip surface and the first main surface of the board.

11. The semiconductor package of claim 10, wherein the resin layer encapsulates at least the terminal bumps and a peripheral portion of the semiconductor chip.

12. A semiconductor package comprising:

a generally rectangular board having oppositely facing first and second main surfaces joined by opposite side edges and opposite end edges;

a wiring circuit including connecting portions on the first main surface;

at least one semiconductor chip mounted on the first main surface of the board; and

flat type external connecting terminals on the second main surface of the board and electrically connected to the semiconductor chip, the flat type external connecting terminals being spaced by linear separating portions perpendicular to the side edges of the board and spaced by at least one curved separating portion extending substantially between the end edges of the board.

13. The semiconductor package of claim 12, wherein at least two of the external connecting terminals include opposite end portions proximate to the opposite end edges of the board and joined by curved portions extending between the opposite end portions and uniformly spaced by the at least one curved separating portion.

14. The semiconductor package of claim 12, wherein the at least one curved separating portion is of generally S-shaped configuration.

15. A semiconductor package, comprising:

a substrate having a first face, a second face, a wiring pattern formed on the first face, and at least one through hole;

at least one semiconductor chip mounted on the first face of the substrate and having an electrode connected to the wiring pattern; and

a conductive layer formed on the second face of the board, the conductive layer having grooves that divide the conductive layer into a plurality of flat type external connecting terminals, the flat type external connecting terminals being connected to the wiring pattern via the through hole, the grooves dividing the conductive layer asymmetrically, and including at least one smoothly curved groove running from a first end of the conductive layer to a second end to the conductive layer.

16. A semiconductor package as set forth in claim 15, wherein the grooves divide the conductive layer in such a manner that all straight lines across the surface of a region to form the flat type external connecting terminals run on at least one of the flat type external connecting terminals.

17. A semiconductor package as set forth in claim 16, wherein the at least one smoothly curved groove is generally S-shaped.

18. A semiconductor package as set forth in claim 15, wherein respective flat type external connecting terminals cover at least a region where the at least one through hole is formed.

19. A semiconductor package as set forth in claim 15, wherein the flat type external connecting terminals have side faces, and any pair of opposed side faces of the flat type external connecting terminals divided by the grooves are substantially parallel.

20. A card shaped storage medium comprising:

a semiconductor package comprising,

a substrate having a first face, a second face, a wiring pattern formed on the first face, and at least one though hole;

at least one semiconductor chip mounted on the first face of the substrate and having an electrode connected to the wiring pattern;

a conductive layer formed on the second face of the board, the conductive layer having grooves that divide the conductive layer into a plurality of flat type external connecting terminals, the flat type external connecting terminals connected to the wiring pattern via the through hole, the grooves dividing the conductive layer asymmetrically, and including at least one smoothly curved groove running from a first end of the conductive layer to a second end of the conductive layer; and

a card for supporting the semiconductor package so that the conductive layer is exposed on a surface of the card.

21. A card shaped storage medium card as set forth in claim 20, wherein the grooves divide the conductive layer in such a manner that all straight lines across the surface of a region including the flat type external connecting terminals run on at least one of the flat type external connecting terminals.

22. A card shaped storage medium as set forth in claim 21, wherein the at least one smoothly curved groove is generally S-shaped.

23. A card shaped storage medium as set forth in claim 20, wherein respective flat type external connecting terminals cover at least regions where through holes are formed.

24. A card shaped storage medium as set forth in claim 20, wherein the flat type external connecting terminals have side faces, and any pair of opposed side faces of the flat type external connecting terminals divided by the grooves are substantially parallel.

25. A card shaped storage medium as set forth in claim 20, wherein the card has a thickness of less than 1 mm.

26. A card shaped storage medium as set forth in claim 20, wherein the board has a thickness in the range from about 0.1 mm to about 0.2 mm.