Buffer circuit

• US 6,054,876 A
• Filed: 07/17/1998
• Issued: 04/25/2000
• Est. Priority Date: 07/18/1997
• Status: Expired due to Term

• Current Assignee: DENSO Corporation
• Original Assignee: DENSO Corporation
• Inventors: Horie, Masakiyo, Isomura, Hirofumi, Harada, Takuya
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): CHO, JAMES HYONCHOL
• Application Number:
  US09/118,072
• Time in Patent Office: 648 Days
• Field of Search: 326/83, 326/86, 326/112, 326/121, 326/119, 326/22, 326/23, 326/26, 326/27, 327/206, 327/437
• US Class Current: 326/83
• CPC Class Codes: H03F 2203/45641 the LC being controlled, e.g. by a signal derived from a non specified place in the dif amp circuit
• CPC Class Codes: H03F 2203/45674 the LC comprising one current mirror
• CPC Class Codes: H03F 3/3032 using two SEPP driving stages
• CPC Class Codes: H03F 3/45183 Long tailed pairs H03F3/4521, H03F3/45237 take precedence
• CPC Class Codes: H03K 19/018521 of complementary type, e.g. CMOS

Abstract

A buffer circuit includes a signal input terminal and a signal output terminal. A first operational amplifier includes a differential amplifier circuit having an input transistor of an N-channel MOS type. The first operational amplifier has an inverting input terminal and an output terminal connected to each other. The first operational amplifier has a non-inverting input terminal connected to the signal input terminal. A second operational amplifier includes a differential amplifier circuit having an input transistor of a P-channel MOS type. The second operational amplifier has an inverting input terminal and an output terminal connected to each other. The second operational amplifier has a non-inverting input terminal connected to the signal input terminal. A first switching device operates for connecting the output terminal of the first operational amplifier to the signal output terminal when a voltage of an input signal applied to the signal input terminal is in a range where the first operational amplifier is operative. A second switching device operates for connecting the output terminal of the second operational amplifier to the signal output terminal when the voltage of the input signal applied to the signal input terminal is in a range where the second operational amplifier is operative.

Claims

1. A buffer circuit comprising:

a signal input terminal;

a signal output terminal;

a first operational amplifier including a differential amplifier circuit having an input transistor of an N-channel MOS type, the first operational amplifier having an inverting input terminal and an output terminal connected to each other, the first operational amplifier having a non-inverting input terminal connected to the signal input terminal;

a second operational amplifier including a differential amplifier circuit having an input transistor of a P-channel MOS type, the second operational amplifier having an inverting input terminal and an output terminal connected to each other, the second operational amplifier having a non-inverting input terminal connected to the signal input terminal;

first switching means for connecting the output terminal of the first operational amplifier to the signal output terminal when a voltage of an input signal applied to the signal input terminal is in a range where the first operational amplifier is operative; and

second switching means for connecting the output terminal of the second operational amplifier to the signal output terminal when the voltage of the input signal applied to the signal input terminal is in a range where the second operational amplifier is operative.

2. A buffer circuit as recited in claim 1, wherein the first switching means comprises:

a first output transistor having a first output terminal connected to the output terminal of the first operational amplifier, and a second output terminal connected to the signal output terminal; and

first drive means for setting the first output transistor in its on state when the voltage of the input signal applied to the signal input terminal is in the range where the first operational amplifier is operative; and

wherein the second switching means comprises;

a second output transistor having a first output terminal connected to the output terminal of the second operational amplifier, and a second output terminal connected to the signal output terminal; and

second drive means for setting the second output transistor in its on state when the voltage of the input signal applied to the signal input terminal is in the range where the second operational amplifier is operative.

3. A buffer circuit as recited in claim 2, wherein the first output transistor comprises a P-channel MOS transistor having a source connected to the output terminal of the first operational amplifier, and a drain connected to the signal output terminal;

wherein the second output transistor comprises an N-channel MOS transistor having a source connected to the output terminal of the second operational amplifier, and a drain connected to the signal output terminal;

wherein the first drive means comprises;

an N-channel MOS transistor having a gate connected to the output terminal of the second operational amplifier or the signal input terminal, a source connected to a lower voltage side of a dc voltage, and a drain connected to a gate of the first output transistor; and

a first load resistor connected between the drain of the N-channel MOS transistor in the first drive means and a higher voltage side of the dc voltage; and

wherein the second drive means comprises;

a P-channel MOS transistor having a gate connected to the output terminal of the first operational amplifier or the signal input terminal, a source connected to the higher voltage side of the dc voltage, and a drain connected to a gate of the second output transistor; and

a second load resistor connected between the drain of the P-channel MOS transistor in the second drive means and the lower voltage side of the dc voltage.

4. A buffer circuit as recited in claim 1, further comprising:

first adjusting means provided in the differential amplifier circuit in the first operational amplifier for adjusting an output voltage of the first operational amplifier in response to a first control voltage;

second adjusting means provided in the differential amplifier circuit in the second operational amplifier for adjusting an output voltage of the second operational amplifier in response to a second control voltage;

reference voltage applying means for applying a prescribed reference voltage to the non-inverting input terminal of the first operational amplifier and the non-inverting input terminal of the second operational amplifier; and

offset correcting means for, in cases where the reference voltage applying means continues to apply the prescribed reference voltage to the non-inverting input terminal of the first operational amplifier and the non-inverting input terminal of the second operational amplifier,

     1) varying the first control voltage to the first adjusting means,

     2) stopping varying the first control voltage when the output voltage of the first operational amplifier becomes equal to the prescribed reference voltage,

     3) varying the second control voltage to the second operational amplifier, and

     4) stopping varying the second control voltage when the output voltage of the second operational amplifier becomes equal to the prescribed reference voltage.

5. A buffer circuit as recited in claim 1, wherein the first switching means comprises a first output transistor having a first output terminal connected to the output terminal of the first operational amplifier, and a second output terminal connected to the signal output terminal;

wherein the second switching means comprises a second output transistor having a first output terminal connected to the output terminal of the second operational amplifier, and a second output terminal connected to the signal output terminal; and

wherein threshold voltages of the first and second output transistors are different from threshold voltages of transistors in the first and second operational amplifiers.

6. A buffer circuit as recited in claim 1, wherein the first switching means comprises a P-channel MOS transistor having a source connected to the output terminal of the first operational amplifier, a drain connected to the signal output terminal, and a gate subjected to a first fixed potential;

and

wherein the second switching means comprises an N-channel MOS transistor having a source connected to the output terminal of the second operational amplifier, a drain connected to the signal output terminal, and a gate subjected to a second fixed potential different from the first fixed potential.