Display unit displaying images at a refresh rate less than the rate at which the images are encoded in a received display signal

• US 6,054,980 A
• Filed: 01/06/1999
• Issued: 04/25/2000
• Est. Priority Date: 01/06/1999
• Status: Expired due to Term

• Current Assignee: Tamiras Per Pte Ltd LLC (Intellectual Ventures LLC)
• Original Assignee: Genesis Microchip Corp (STMicroelectronics NV)
• Inventors: Eglit, Alexander Julian
• Primary Examiner(s): Saras, Steven J.
• Assistant Examiner(s): Alphonse, Fritz
• Application Number:
  US09/227,284
• Time in Patent Office: 475 Days
• Field of Search: 345/204, 345/132, 345/202, 345/203, 345/97, 345/516, 348/441, 386/109
• US Class Current: 345/204
• CPC Class Codes: G09G 2340/0435 Change or adaptation of the frame rate of the video stream
• CPC Class Codes: G09G 5/393 Arrangements for updating the contents of the bit-mapped memory
• CPC Class Codes: G09G 5/395 Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen G09G5/399 takes precedence

Abstract

A display unit receiving a display signal having source image frames encoded at an encoding rate (FR_S). A display screen may be refreshed at a refresh rate which is less than the encoding rate. An actual refresh rate (FR_D) is determined such that FR_S /FR_D =(N+1)/N. To satisfy this equation, the actual refresh rate (FR_D) may be selected to be slightly different from the target refresh rate supported by the display screen. Pixel data elements representing source image frames (received at FR_S) may be written into a frame buffer, and the pixel data elements may be retrieved at a frequency determined by refresh rate FR_D. However, at least a part of every (N+1)^st source image frame is not written into the frame buffer to avoid image tearing problems.

Claims

1. A method of displaying images according to a plurality of source image frames encoded in a display signal, said source image frames being encoded at an encoding frequency FR_S and said images being displayed on a display screen of a display unit, wherein said display unit has an associated target refresh rate, wherein said encoding frequency is greater than said target refresh rate, said method comprising the steps of:

(a) receiving said analog display signal in said display unit;

(b) determining an actual refresh rate FR_D and N such that, FR_S /FR_D =(N+1)/N, wherein FR_D is at least approximately equal to said target refresh rate and N in an integer greater than or equal to 2;

(c) generating a plurality of pixel data elements representing each of said source image frames;

(d) storing said plurality of pixel data elements in a frame buffer;

(e) retrieving said plurality of pixel data elements from said frame buffer such that said display screen can be refreshed at FR_D ; and

(f) disabling the storing of at least some of said plurality of pixel data elements related to every (N+1)^st source image frame into said frame of step (d),

wherein step (f) prevents image tearing problem by ensuring that a single display image is not generated from two source images.

2. The method of claim 1, wherein said frame buffer comprises sufficient memory space to store pixel data elements corresponding to one source image frame.

3. The method of claim 2, wherein said display unit comprises a digital display unit and said display signal comprises an analog display signal.

4. The method of claim 2, wherein step (f) comprises the step of disabling the storing of said pixel data elements related to every (N+1)^st frame.

5. The method of claim 2, wherein said target refresh rate equals 60 Hz, said encoding rate equals 66 Hz, and said actual refresh rate is chosen to equal said target refresh rate such that N=10.

6. The method of claim 2, wherein said target refresh rate equals 60 Hz, said encoding rate equals 70 Hz, and said actual refresh rate is chosen to equal said target refresh rate such that N=6.

7. The method of claim 2, wherein said target refresh rate equals 60 Hz, said encoding rate equals 72 Hz, and said actual refresh rate is chosen to equal said target refresh rate such that N=5.

8. The method of claim 2, wherein said target refresh rate equals 60 Hz, said encoding rate equals 75 Hz, and said actual refresh rate is chosen to equal said target refresh rate such that N=4.

9. The method of claim 2, wherein said target refresh rate equals 60 Hz, said encoding rate equals 90 Hz, and said actual refresh rate is chosen to equal said target refresh rate such that N=2.

10. The method of claim 2, wherein said target refresh rate equals 60 Hz, said encoding rate equals 85 Hz, and said actual refresh rate is chosen to equal 56.67 Hz such that N=2.

11. The method of claim 2, wherein said target refresh rate equals 60 Hz, said encoding rate equals 87 Hz, and said actual refresh rate is chosen to equal 58 Hz such that N=2.

12. The method of claim 2, wherein said display signal comprises a digital display signal.

13. A display circuit for generating display signals on a display screen provided in a display unit, wherein a target refresh rate is associated with said display screen, said display circuit comprising:

a data recovery block for receiving a display signal containing a plurality of source image frames, wherein said source image frames are encoded at an encoding rate, said Data recovery block generating a plurality of pixel data elements representing each of said source image frames;

a frame buffer coupled to said data recovery block, said frame buffer for storing said plurality of pixel data elements;

a control circuit for determining an actual refresh rate FR_D and an integer N such that, FR_S /FR_D =(N+1)/N, wherein FR_D is at least approximately equal to said target refresh rate, said control circuit disabling the storing of at least some of said plurality of pixel data elements related to every (N+1)^st source image frame;

a display interface for receiving said plurality of pixel data elements stored in said frame buffer and refreshing said display screen at said actual refresh rate,

wherein disabling storing of every (N+1)^st source image frame enables said display circuit to avoid image tearing on said display screen.

14. The display circuit of claim 13, wherein said frame buffer comprises a random access memory with a single port for read accesses and write accesses.

15. The display circuit of claim 13, wherein said frame buffer comprises sufficient memory space to store pixel data elements corresponding to one source image frame.

16. The display circuit of claim 13, wherein said control circuit comprises:

a cycle counter for counting the number of source image frames received in said display signal;

a comparator for comparing the output of said cycle counter with the value N and generating a reset signal for said cycle counter when an equality of detected, said reset signal resetting said cycle counter to zero,

wherein the output of said comparator is provided as a write enable signal to said frame buffer, wherein pixel data elements are stored in said frame buffer when said write enable signal is at one logical level and storing is disabled when said write enable signal is in a second logical level.

17. The display circuit of claim 13, wherein said control circuit comprises:

a write address counter for generating a write address for storing each of said pixel data elements into said frame buffer, wherein said write address counter is clocked by a sampling clock provided to said Data recovery block also, said write address counter being reset to zero by a vertical synchronization signal;

a last address register coupled to the output of said write address counter, wherein said last address register stores the write address generated by said write address counter when said vertical synchronization signal is received;

a read address counter for generating a read address for retrieving pixel data elements from said frame buffer, wherein said retrieved data is provided to said display interface; and

a comparator for comparing the address stored in said last address register with said address generated by said read address counter, said comparator resetting said read address counter to zero upon detecting an equality.

18. The display circuit of claim 13, wherein said display circuit is provided as an integrated circuit.

19. A digital display unit for displaying images represented by a plurality of source image frames, wherein said source image frames are encoded in a display signal at an encoding rate, said digital display unit comprising:

a display screen having a target refresh rate which is less than said encoding rate;

a data recovery block for receiving said display signal, said data recovery block generating a plurality of pixel data elements representing each of said source image frames;

a frame buffer coupled to said data recovery block, said frame buffer for storing said plurality of pixel data elements;

a control circuit for determining an actual refresh rate FR_D and an integer N such that, FR_S /FR_D =(N+1)/N, wherein FR_D is at least approximately equal to said target refresh rate, said control circuit disabling the storing of at least some of said plurality of pixel data elements related to every (N+1)^st source image frame;

a display interface for receiving said plurality of pixel data elements stored in said frame buffer and refreshing said display screen at said actual refresh rate,

wherein disabling storing of every (N+1)^st source image frame enables said display circuit to avoid image tearing on said display screen.

20. The display unit of claim 19, wherein said display signal comprises an analog display signal and said data recovery block comprises an analog-to-digital converter (ADC).

21. The display unit of claim 19, wherein said frame buffer comprises sufficient memory capacity to store pixel data elements related to one source image frame.

22. A display unit for displaying images according to a plurality of source image frames encoded in a display signal, said display unit including a display screen designed to support a target refresh rate, said display unit comprising:

receiving means for receiving said display signal in said display unit;

means for determining an actual refresh rate FR_D and an integer N such that, FR_S /FR_D =(N+1)/N, wherein FR_D is at least approximately equal to said target refresh rate;

means for generating a plurality of pixel data elements representing each of said source image frames;

storage means for storing said plurality of pixel data elements in a frame buffer;

means for retrieving said plurality of pixel data elements from said frame buffer such that said display screen can be refreshed at FR_D ; and

means for disabling the storing of at least some of said plurality of pixel data elements related to every (N+1)^st source image frame into said frame buffer,

wherein said disabling prevents image tearing problem by ensuring that a single display image is not generated from two source images.

23. The display unit of claim 22, wherein said frame buffer comprises sufficient memory capacity to store pixel data elements related to one source image frame.